kegel/IMUIdentifier/debug.svd

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<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
<vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
<vendorID>ESPRESSIF</vendorID>
<name>ESP32</name>
<series>ESP32</series>
<version>8</version>
<description>32-bit MCU &amp; 2.4 GHz Wi-Fi &amp; Bluetooth/Bluetooth LE</description>
<licenseText>
Copyright 2022 Espressif Systems (Shanghai) PTE LTD
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
</licenseText>
<cpu>
<name>Xtensa LX6</name>
<revision>r0p0</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>32</addressUnitBits>
<width>32</width>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral>
<name>AES</name>
<description>AES (Advanced Encryption Standard) Accelerator</description>
<groupName>AES</groupName>
<baseAddress>0x3FF01000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x40</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>START</name>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>START</name>
<description>Write 1 to start the AES operation.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>IDLE</name>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>IDLE</name>
<description>AES Idle register. Reads zero while the AES Accelerator is busy processing; reads one otherwise.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>MODE</name>
<description>Selects the AES accelerator mode of operation. See Table 22-1 for details.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>8</dim>
<dimIncrement>0x4</dimIncrement>
<name>KEY_%s</name>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>KEY</name>
<description>AES key material register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<name>TEXT_%s</name>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>TEXT</name>
<description>Plaintext and ciphertext register.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ENDIAN</name>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>ENDIAN</name>
<description>Endianness selection register. See Table 22-2 for details.</description>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>APB_CTRL</name>
<description>Advanced Peripheral Bus Controller</description>
<groupName>APB_CTRL</groupName>
<baseAddress>0x3FF66000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x44</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYSCLK_CONF</name>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<resetValue>0x00002000</resetValue>
<fields>
<field>
<name>PRE_DIV_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLK_320M_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CLK_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RST_TICK_CNT</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>QUICK_CLK_CHNG</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>XTAL_TICK_CONF</name>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<resetValue>0x00000027</resetValue>
<fields>
<field>
<name>XTAL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PLL_TICK_CONF</name>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<resetValue>0x0000004F</resetValue>
<fields>
<field>
<name>PLL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CK8M_TICK_CONF</name>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<resetValue>0x0000000B</resetValue>
<fields>
<field>
<name>CK8M_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_CTRL</name>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<resetValue>0x007F8240</resetValue>
<fields>
<field>
<name>SARADC_START_FORCE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_START</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR2_MUX</name>
<description>1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_WORK_MODE</name>
<description>0: single mode 1: double mode 2: alternate mode</description>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR_SEL</name>
<description>0: SAR1 1: SAR2 only work for single SAR mode</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR_CLK_GATED</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR_CLK_DIV</name>
<description>SAR clock divider</description>
<bitOffset>7</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR1_PATT_LEN</name>
<description>0 ~ 15 means length 1 ~ 16</description>
<bitOffset>15</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR2_PATT_LEN</name>
<description>0 ~ 15 means length 1 ~ 16</description>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR1_PATT_P_CLEAR</name>
<description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR2_PATT_P_CLEAR</name>
<description>clear the pointer of pattern table for DIG ADC2 CTRL</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_DATA_SAR_SEL</name>
<description>1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_DATA_TO_I2S</name>
<description>1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix</description>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_CTRL2</name>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<resetValue>0x000001FE</resetValue>
<fields>
<field>
<name>SARADC_MEAS_NUM_LIMIT</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_MAX_MEAS_NUM</name>
<description>max conversion number</description>
<bitOffset>1</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR1_INV</name>
<description>1: data to DIG ADC1 CTRL is inverted otherwise not</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAR2_INV</name>
<description>1: data to DIG ADC2 CTRL is inverted otherwise not</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_FSM</name>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<resetValue>0x0208FF08</resetValue>
<fields>
<field>
<name>SARADC_RSTB_WAIT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_STANDBY_WAIT</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_START_WAIT</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SARADC_SAMPLE_CYCLE</name>
<description>sample cycles</description>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB1</name>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB1</name>
<description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB2</name>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB2</name>
<description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB3</name>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB3</name>
<description>Item 8 ~ 11 for pattern table 1 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB4</name>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB4</name>
<description>Item 12 ~ 15 for pattern table 1 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB1</name>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB1</name>
<description>item 0 ~ 3 for pattern table 2 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB2</name>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB2</name>
<description>Item 4 ~ 7 for pattern table 2 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB3</name>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB3</name>
<description>Item 8 ~ 11 for pattern table 2 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB4</name>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<resetValue>0x0F0F0F0F</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB4</name>
<description>Item 12 ~ 15 for pattern table 2 (each item one byte)</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APLL_TICK_CONF</name>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<resetValue>0x00000063</resetValue>
<fields>
<field>
<name>APLL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<resetValue>0x16042000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>BB</name>
<description>Peripheral BB</description>
<groupName>BB</groupName>
<baseAddress>0x3FF5D000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>BBPD_CTRL</name>
<description>Baseband control register</description>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>DC_EST_FORCE_PD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DC_EST_FORCE_PU</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FFT_FORCE_PD</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FFT_FORCE_PU</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>DPORT</name>
<description>Peripheral DPORT</description>
<groupName>DPORT</groupName>
<baseAddress>0x3FF00000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0x5C0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>WIFI_MAC</name>
<value>0</value>
</interrupt>
<interrupt>
<name>WIFI_NMI</name>
<value>1</value>
</interrupt>
<interrupt>
<name>WIFI_BB</name>
<value>2</value>
</interrupt>
<interrupt>
<name>BT_MAC</name>
<value>3</value>
</interrupt>
<interrupt>
<name>BT_BB</name>
<value>4</value>
</interrupt>
<interrupt>
<name>BT_BB_NMI</name>
<value>5</value>
</interrupt>
<interrupt>
<name>RWBT</name>
<value>6</value>
</interrupt>
<interrupt>
<name>RWBLE</name>
<value>7</value>
</interrupt>
<interrupt>
<name>RWBT_NMI</name>
<value>8</value>
</interrupt>
<interrupt>
<name>RWBLE_NMI</name>
<value>9</value>
</interrupt>
<registers>
<register>
<name>PRO_BOOT_REMAP_CTRL</name>
<addressOffset>0x0</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO_BOOT_REMAP</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_BOOT_REMAP_CTRL</name>
<addressOffset>0x4</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APP_BOOT_REMAP</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ACCESS_CHECK</name>
<addressOffset>0x8</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>APP</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PRO_DPORT_APB_MASK0</name>
<addressOffset>0xC</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRODPORT_APB_MASK0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_DPORT_APB_MASK1</name>
<addressOffset>0x10</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRODPORT_APB_MASK1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_DPORT_APB_MASK0</name>
<addressOffset>0x14</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APPDPORT_APB_MASK0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_DPORT_APB_MASK1</name>
<addressOffset>0x18</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APPDPORT_APB_MASK1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PERI_CLK_EN</name>
<addressOffset>0x1C</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PERI_CLK_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PERI_RST_EN</name>
<addressOffset>0x20</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PERI_RST_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WIFI_BB_CFG</name>
<addressOffset>0x24</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>WIFI_BB_CFG</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WIFI_BB_CFG_2</name>
<addressOffset>0x28</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>WIFI_BB_CFG_2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_A</name>
<addressOffset>0x2C</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>APPCPU_RESETTING</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_B</name>
<addressOffset>0x30</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APPCPU_CLKGATE_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_C</name>
<addressOffset>0x34</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APPCPU_RUNSTALL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_D</name>
<addressOffset>0x38</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APPCPU_BOOT_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPU_PER_CONF</name>
<addressOffset>0x3C</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>CPUPERIOD_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LOWSPEED_CLK_SEL</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FAST_CLK_RTC_SEL</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_CTRL</name>
<addressOffset>0x40</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_CACHE_MODE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_ENABLE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_FLUSH_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_FLUSH_DONE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PRO_CACHE_LOCK_0_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_LOCK_1_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_LOCK_2_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_LOCK_3_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_SINGLE_IRAM_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_DRAM_SPLIT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_AHB_SPI_REQ</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PRO_SLAVE_REQ</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>AHB_SPI_REQ</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>SLAVE_REQ</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PRO_DRAM_HL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_CTRL1</name>
<addressOffset>0x44</addressOffset>
<size>0x20</size>
<resetValue>0x000008FF</resetValue>
<fields>
<field>
<name>PRO_CACHE_MASK_IRAM0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_MASK_IRAM1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_MASK_IROM0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_MASK_DRAM1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_MASK_DROM0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_MASK_OPSDRAM</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CMMU_SRAM_PAGE_MODE</name>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CMMU_FLASH_PAGE_MODE</name>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CMMU_FORCE_ON</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CMMU_PD</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_MMU_IA_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_0_ADDR</name>
<addressOffset>0x48</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_1_ADDR</name>
<addressOffset>0x4C</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_2_ADDR</name>
<addressOffset>0x50</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_3_ADDR</name>
<addressOffset>0x54</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_CTRL</name>
<addressOffset>0x58</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>APP_CACHE_MODE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_ENABLE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_FLUSH_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_FLUSH_DONE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>APP_CACHE_LOCK_0_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_LOCK_1_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_LOCK_2_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_LOCK_3_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_SINGLE_IRAM_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_DRAM_SPLIT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_AHB_SPI_REQ</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>APP_SLAVE_REQ</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>APP_DRAM_HL</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_CTRL1</name>
<addressOffset>0x5C</addressOffset>
<size>0x20</size>
<resetValue>0x000008FF</resetValue>
<fields>
<field>
<name>APP_CACHE_MASK_IRAM0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_MASK_IRAM1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_MASK_IROM0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_MASK_DRAM1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_MASK_DROM0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_MASK_OPSDRAM</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CMMU_SRAM_PAGE_MODE</name>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CMMU_FLASH_PAGE_MODE</name>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CMMU_FORCE_ON</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CMMU_PD</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_MMU_IA_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_0_ADDR</name>
<addressOffset>0x60</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_1_ADDR</name>
<addressOffset>0x64</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_2_ADDR</name>
<addressOffset>0x68</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_3_ADDR</name>
<addressOffset>0x6C</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TRACEMEM_MUX_MODE</name>
<addressOffset>0x70</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>TRACEMEM_MUX_MODE</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TRACEMEM_ENA</name>
<addressOffset>0x74</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO_TRACEMEM_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>APP_TRACEMEM_ENA</name>
<addressOffset>0x78</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APP_TRACEMEM_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CACHE_MUX_MODE</name>
<addressOffset>0x7C</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>CACHE_MUX_MODE</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IMMU_PAGE_MODE</name>
<addressOffset>0x80</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>INTERNAL_SRAM_IMMU_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>IMMU_PAGE_MODE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>DMMU_PAGE_MODE</name>
<addressOffset>0x84</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>INTERNAL_SRAM_DMMU_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMMU_PAGE_MODE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ROM_MPU_ENA</name>
<addressOffset>0x88</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>SHARE_ROM_MPU_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_ROM_MPU_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_ROM_MPU_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>MEM_PD_MASK</name>
<addressOffset>0x8C</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>LSLP_MEM_PD_MASK</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ROM_PD_CTRL</name>
<addressOffset>0x90</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO_ROM_PD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_ROM_PD</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SHARE_ROM_PD</name>
<bitOffset>2</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>ROM_FO_CTRL</name>
<addressOffset>0x94</addressOffset>
<size>0x20</size>
<resetValue>0x00000003</resetValue>
<fields>
<field>
<name>PRO_ROM_FO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_ROM_FO</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SHARE_ROM_FO</name>
<bitOffset>2</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRAM_PD_CTRL_0</name>
<addressOffset>0x98</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>SRAM_PD_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRAM_PD_CTRL_1</name>
<addressOffset>0x9C</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>SRAM_PD_1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRAM_FO_CTRL_0</name>
<addressOffset>0xA0</addressOffset>
<size>0x20</size>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>SRAM_FO_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SRAM_FO_CTRL_1</name>
<addressOffset>0xA4</addressOffset>
<size>0x20</size>
<resetValue>0x00000001</resetValue>
<fields>
<field>
<name>SRAM_FO_1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IRAM_DRAM_AHB_SEL</name>
<addressOffset>0xA8</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>MASK_PRO_IRAM</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MASK_APP_IRAM</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MASK_PRO_DRAM</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MASK_APP_DRAM</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MASK_AHB</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAC_DUMP_MODE</name>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>TAG_FO_CTRL</name>
<addressOffset>0xAC</addressOffset>
<size>0x20</size>
<resetValue>0x00000101</resetValue>
<fields>
<field>
<name>PRO_CACHE_TAG_FORCE_ON</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRO_CACHE_TAG_PD</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_TAG_FORCE_ON</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP_CACHE_TAG_PD</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AHB_LITE_MASK</name>
<addressOffset>0xB0</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APP</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SDIO</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PRODPORT</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>APPDPORT</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>AHB_LITE_SDHOST_PID</name>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AHB_MPU_TABLE_0</name>
<addressOffset>0xB4</addressOffset>
<size>0x20</size>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>AHB_ACCESS_GRANT_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>AHB_MPU_TABLE_1</name>
<addressOffset>0xB8</addressOffset>
<size>0x20</size>
<resetValue>0x000001FF</resetValue>
<fields>
<field>
<name>AHB_ACCESS_GRANT_1</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>HOST_INF_SEL</name>
<addressOffset>0xBC</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PERI_IO_SWAP</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LINK_DEVICE_SEL</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PERIP_CLK_EN</name>
<addressOffset>0xC0</addressOffset>
<size>0x20</size>
<resetValue>0xF9C1E06F</resetValue>
<fields>
<field>
<name>TIMERS_CLK_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI01_CLK_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART_CLK_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDG_CLK_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2S0_CLK_EN</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART1_CLK_EN</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI2_CLK_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2C0_EXT0_CLK_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UHCI0_CLK_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMT_CLK_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PCNT_CLK_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LEDC_CLK_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UHCI1_CLK_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TIMERGROUP_CLK_EN</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EFUSE_CLK_EN</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TIMERGROUP1_CLK_EN</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI3_CLK_EN</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM0_CLK_EN</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2C_EXT1_CLK_EN</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TWAI_CLK_EN</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM1_CLK_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2S1_CLK_EN</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI_DMA_CLK_EN</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART2_CLK_EN</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART_MEM_CLK_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM2_CLK_EN</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM3_CLK_EN</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PERIP_RST_EN</name>
<addressOffset>0xC4</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>TIMERS_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI01_RST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART_RST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WDG_RST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2S0_RST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART1_RST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI2_RST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2C0_EXT0_RST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UHCI0_RST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RMT_RST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PCNT_RST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LEDC_RST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UHCI1_RST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TIMERGROUP_RST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EFUSE_RST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TIMERGROUP1_RST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI3_RST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM0_RST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2C_EXT1_RST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TWAI_RST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM1_RST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>I2S1_RST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI_DMA_RST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART2_RST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>UART_MEM_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM2_RST</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PWM3_RST</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>SLAVE_SPI_CONFIG</name>
<addressOffset>0xC8</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>SLAVE_SPI_MASK_PRO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SLAVE_SPI_MASK_APP</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI_ENCRYPT_ENABLE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPI_DECRYPT_ENABLE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>WIFI_CLK_EN</name>
<addressOffset>0xCC</addressOffset>
<size>0x20</size>
<resetValue>0xFFFCE030</resetValue>
<fields>
<field>
<name>WIFI_CLK_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WIFI_CLK_WIFI_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WIFI_CLK_WIFI_BT_COMMON</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WIFI_CLK_BT_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CORE_RST_EN</name>
<addressOffset>0xD0</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>CORE_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BB_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FE_RST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MAC_RST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BT_RST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTMAC_RST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SDIO_RST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SDIO_HOST_RST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EMAC_RST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>MACPWR_RST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RW_BTMAC_RST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RW_BTLP_RST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BT_LPCK_DIV_INT</name>
<addressOffset>0xD4</addressOffset>
<size>0x20</size>
<resetValue>0x000000FF</resetValue>
<fields>
<field>
<name>BT_LPCK_DIV_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BTEXTWAKEUP_REQ</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>BT_LPCK_DIV_FRAC</name>
<addressOffset>0xD8</addressOffset>
<size>0x20</size>
<resetValue>0x02001001</resetValue>
<fields>
<field>
<name>BT_LPCK_DIV_B</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BT_LPCK_DIV_A</name>
<bitOffset>12</bitOffset>
<bitWidth>12</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPCLK_SEL_RTC_SLOW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPCLK_SEL_8M</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPCLK_SEL_XTAL</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>LPCLK_SEL_XTAL32K</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_0</name>
<addressOffset>0xDC</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_1</name>
<addressOffset>0xE0</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_2</name>
<addressOffset>0xE4</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_2</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_3</name>
<addressOffset>0xE8</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_3</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_INTR_STATUS_0</name>
<addressOffset>0xEC</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO_INTR_STATUS_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PRO_INTR_STATUS_1</name>
<addressOffset>0xF0</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO_INTR_STATUS_1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PRO_INTR_STATUS_2</name>
<addressOffset>0xF4</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>PRO_INTR_STATUS_2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>APP_INTR_STATUS_0</name>
<addressOffset>0xF8</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APP_INTR_STATUS_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>APP_INTR_STATUS_1</name>
<addressOffset>0xFC</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APP_INTR_STATUS_1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>APP_INTR_STATUS_2</name>
<addressOffset>0x100</addressOffset>
<size>0x20</size>
<fields>
<field>
<name>APP_INTR_STATUS_2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>PRO_MAC_INTR_MAP</name>
<addressOffset>0x104</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_MAC_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_MAC_NMI_MAP</name>
<addressOffset>0x108</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_MAC_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_BB_INT_MAP</name>
<addressOffset>0x10C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_BB_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_BT_MAC_INT_MAP</name>
<addressOffset>0x110</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_BT_MAC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_BT_BB_INT_MAP</name>
<addressOffset>0x114</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_BT_BB_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_BT_BB_NMI_MAP</name>
<addressOffset>0x118</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_BT_BB_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_RWBT_IRQ_MAP</name>
<addressOffset>0x11C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_RWBT_IRQ_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_RWBLE_IRQ_MAP</name>
<addressOffset>0x120</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_RWBLE_IRQ_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_RWBT_NMI_MAP</name>
<addressOffset>0x124</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_RWBT_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_RWBLE_NMI_MAP</name>
<addressOffset>0x128</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_RWBLE_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SLC0_INTR_MAP</name>
<addressOffset>0x12C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SLC0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SLC1_INTR_MAP</name>
<addressOffset>0x130</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SLC1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_UHCI0_INTR_MAP</name>
<addressOffset>0x134</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_UHCI0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_UHCI1_INTR_MAP</name>
<addressOffset>0x138</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_UHCI1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG_T0_LEVEL_INT_MAP</name>
<addressOffset>0x13C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG_T0_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG_T1_LEVEL_INT_MAP</name>
<addressOffset>0x140</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG_T1_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG_WDT_LEVEL_INT_MAP</name>
<addressOffset>0x144</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG_WDT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG_LACT_LEVEL_INT_MAP</name>
<addressOffset>0x148</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG_LACT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_T0_LEVEL_INT_MAP</name>
<addressOffset>0x14C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG1_T0_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_T1_LEVEL_INT_MAP</name>
<addressOffset>0x150</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG1_T1_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
<addressOffset>0x154</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
<addressOffset>0x158</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_GPIO_INTERRUPT_MAP</name>
<addressOffset>0x15C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_GPIO_INTERRUPT_PRO_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_GPIO_INTERRUPT_NMI_MAP</name>
<addressOffset>0x160</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_GPIO_INTERRUPT_PRO_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
<addressOffset>0x164</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
<addressOffset>0x168</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
<addressOffset>0x16C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
<addressOffset>0x170</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_0_MAP</name>
<addressOffset>0x174</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_0_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_1_MAP</name>
<addressOffset>0x178</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_2_MAP</name>
<addressOffset>0x17C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_3_MAP</name>
<addressOffset>0x180</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_3_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_I2S0_INT_MAP</name>
<addressOffset>0x184</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_I2S0_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_I2S1_INT_MAP</name>
<addressOffset>0x188</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_I2S1_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_UART_INTR_MAP</name>
<addressOffset>0x18C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_UART_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_UART1_INTR_MAP</name>
<addressOffset>0x190</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_UART1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_UART2_INTR_MAP</name>
<addressOffset>0x194</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_UART2_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
<addressOffset>0x198</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_EMAC_INT_MAP</name>
<addressOffset>0x19C</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_EMAC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_PWM0_INTR_MAP</name>
<addressOffset>0x1A0</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_PWM0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_PWM1_INTR_MAP</name>
<addressOffset>0x1A4</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_PWM1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_PWM2_INTR_MAP</name>
<addressOffset>0x1A8</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_PWM2_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_PWM3_INTR_MAP</name>
<addressOffset>0x1AC</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_PWM3_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_LEDC_INT_MAP</name>
<addressOffset>0x1B0</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_LEDC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_EFUSE_INT_MAP</name>
<addressOffset>0x1B4</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_EFUSE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_CAN_INT_MAP</name>
<addressOffset>0x1B8</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_CAN_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_RTC_CORE_INTR_MAP</name>
<addressOffset>0x1BC</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_RTC_CORE_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_RMT_INTR_MAP</name>
<addressOffset>0x1C0</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_RMT_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_PCNT_INTR_MAP</name>
<addressOffset>0x1C4</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_PCNT_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_I2C_EXT0_INTR_MAP</name>
<addressOffset>0x1C8</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_I2C_EXT0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_I2C_EXT1_INTR_MAP</name>
<addressOffset>0x1CC</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_I2C_EXT1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_RSA_INTR_MAP</name>
<addressOffset>0x1D0</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_RSA_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SPI1_DMA_INT_MAP</name>
<addressOffset>0x1D4</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SPI1_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SPI2_DMA_INT_MAP</name>
<addressOffset>0x1D8</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SPI2_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_SPI3_DMA_INT_MAP</name>
<addressOffset>0x1DC</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_SPI3_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_WDG_INT_MAP</name>
<addressOffset>0x1E0</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_WDG_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>PRO_TIMER_INT1_MAP</name>
<addressOffset>0x1E4</addressOffset>
<size>0x20</size>
<resetValue>0x00000010</resetValue>
<fields>
<field>
<name>PRO_TIMER_INT1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>