[Controller] Added board config for custom controller STeMCell (#16287)
Co-authored-by: Mariappan Ramasamy <947300+Mariappan@users.noreply.github.com> Co-authored-by: Mariappan Ramasamy <maari@basis-ai.com> Co-authored-by: Sadek Baroudi <sadekbaroudi@gmail.com>master
Mega Mind
GitHub
parent
ba04ecfabd
commit
fce99f3875
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@ -212,7 +212,7 @@ else
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ifeq ($(PLATFORM),AVR)
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# Automatically provided by avr-libc, nothing required
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else ifeq ($(PLATFORM),CHIBIOS)
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ifneq ($(filter STM32F3xx_% STM32F1xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),)
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ifneq ($(filter STM32F3xx_% STM32F1xx_% STM32F4xx_% %_STM32F401xC %_STM32F401xE %_STM32F405xG %_STM32F411xE %_STM32F072xB %_STM32F042x6 %_GD32VF103xB %_GD32VF103x8, $(MCU_SERIES)_$(MCU_LDSCRIPT)),)
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# Emulated EEPROM
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OPT_DEFS += -DEEPROM_DRIVER -DEEPROM_STM32_FLASH_EMULATED
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COMMON_VPATH += $(PLATFORM_PATH)/$(PLATFORM_KEY)/$(DRIVER_DIR)/flash
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@ -54,6 +54,12 @@
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"processor": "STM32F411",
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"bootloader": "stm32-dfu",
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"board": "BLACKPILL_STM32_F411"
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},
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"stemcell": {
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"processor": "STM32F411",
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"bootloader": "tinyuf2",
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"board": "STEMCELL",
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"pin_compatible": "promicro"
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}
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}
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}
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@ -15,6 +15,7 @@ Currently the following converters are available:
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| `promicro` | `promicro_rp2040` |
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| `promicro` | `blok` |
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| `promicro` | `bit_c_pro` |
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| `promicro` | `stemcell` |
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See below for more in depth information on each converter.
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@ -56,6 +57,7 @@ If a board currently supported in QMK uses a [Pro Micro](https://www.sparkfun.co
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| [SparkFun Pro Micro - RP2040](https://www.sparkfun.com/products/18288) | `promicro_rp2040` |
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| [Blok](https://boardsource.xyz/store/628b95b494dfa308a6581622) | `blok` |
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| [Bit-C PRO](https://nullbits.co/bit-c-pro) | `bit_c_pro` |
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| [STeMCell](https://github.com/megamind4089/STeMCell) | `stemcell` |
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Converter summary:
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@ -66,6 +68,7 @@ Converter summary:
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| `promicro_rp2040` | `-e CONVERT_TO=promicro_rp2040` | `CONVERT_TO=promicro_rp2040` | `#ifdef CONVERT_TO_PROMICRO_RP2040` |
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| `blok` | `-e CONVERT_TO=blok` | `CONVERT_TO=blok` | `#ifdef CONVERT_TO_BLOK` |
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| `bit_c_pro` | `-e CONVERT_TO=bit_c_pro` | `CONVERT_TO=bit_c_pro` | `#ifdef CONVERT_TO_BIT_C_PRO` |
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| `stemcell` | `-e CONVERT_TO=stemcell` | `CONVERT_TO=stemcell` | `#ifdef CONVERT_TO_STEMCELL` |
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### Proton C :id=proton_c
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@ -99,3 +102,22 @@ The following defaults are based on what has been implemented for [RP2040](platf
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### SparkFun Pro Micro - RP2040, Blok, and Bit-C PRO :id=promicro_rp2040
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Currently identical to [Adafruit KB2040](#kb2040).
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### STeMCell :id=stemcell
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Feature set currently identical to [Proton C](#proton_c).
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There are two versions of STeMCell available, with different pinouts:
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- v1.0.0
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- v2.0.0 (pre-release v1.0.1, v1.0.2)
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Default official firmware only supports v2.0.0 STeMCell.
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STeMCell has support to swap UART and I2C pins, to enable single-wire uart communication in STM chips.
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The following additional flags has to be used while compiling, based on the pin used for split communication.
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| Split Pin | Compile flags |
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|-----------|---------------|
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| D3 | -e STMC_US=yes|
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| D2 | Not needed |
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| D1 | -e STMC_IS=yes|
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| D0 | Not needed |
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@ -0,0 +1,15 @@
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# Copyright 2022 Mega Mind (@megamind4089)
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Default pin config of nucleo64_411re has most pins in input pull up mode
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# List of all the board related files.
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BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
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# Required include directories
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BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
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# Shared variables
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ALLCSRC += $(BOARDSRC)
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ALLINC += $(BOARDINC)
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@ -0,0 +1,8 @@
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include_next "board.h"
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#undef STM32_HSE_BYPASS
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@ -0,0 +1,9 @@
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#define CH_CFG_ST_RESOLUTION 16
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#define CH_CFG_ST_FREQUENCY 10000
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#include_next <chconf.h>
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@ -0,0 +1,29 @@
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// Copyright 2022 Mega Mind(@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
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# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
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#endif
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/**======================
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** I2C Driver
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*========================**/
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#if !defined(I2C1_SDA_PIN)
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# define I2C1_SDA_PIN D0
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#endif
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#if !defined(I2C1_SCL_PIN)
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# define I2C1_SCL_PIN D1
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#endif
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/**======================
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** SERIAL Driver
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*========================**/
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#if !defined(SERIAL_USART_DRIVER)
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# define SERIAL_USART_DRIVER SD2
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#endif
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@ -0,0 +1,11 @@
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#define PAL_USE_WAIT TRUE
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#define PAL_USE_CALLBACKS TRUE
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#define HAL_USE_I2C TRUE
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#define HAL_USE_SERIAL TRUE
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#include_next <halconf.h>
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@ -0,0 +1,231 @@
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* STM32F4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define STM32F4xx_MCUCONF
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#define STM32F411_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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#define STM32_HSI_ENABLED TRUE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED TRUE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_CLOCK48_REQUIRED TRUE
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLM_VALUE 8
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#define STM32_PLLN_VALUE 336
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#define STM32_PLLP_VALUE 4
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#define STM32_PLLQ_VALUE 7
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#define STM32_RTCPRE_VALUE 8
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#define STM32_MCO1SEL STM32_MCO1SEL_HSI
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#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
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#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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/*
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* IRQ system settings.
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*/
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#define STM32_IRQ_EXTI0_PRIORITY 6
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#define STM32_IRQ_EXTI1_PRIORITY 6
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#define STM32_IRQ_EXTI2_PRIORITY 6
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#define STM32_IRQ_EXTI3_PRIORITY 6
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#define STM32_IRQ_EXTI4_PRIORITY 6
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#define STM32_IRQ_EXTI5_9_PRIORITY 6
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#define STM32_IRQ_EXTI16_PRIORITY 6
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#define STM32_IRQ_EXTI17_PRIORITY 15
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#define STM32_IRQ_EXTI18_PRIORITY 6
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#define STM32_IRQ_EXTI19_PRIORITY 6
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#define STM32_IRQ_EXTI20_PRIORITY 6
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#define STM32_IRQ_EXTI21_PRIORITY 15
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#define STM32_IRQ_EXTI22_PRIORITY 15
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#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
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#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
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#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
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#define STM32_IRQ_TIM1_CC_PRIORITY 7
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#define STM32_IRQ_TIM2_PRIORITY 7
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#define STM32_IRQ_TIM3_PRIORITY 7
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#define STM32_IRQ_TIM4_PRIORITY 7
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#define STM32_IRQ_TIM5_PRIORITY 7
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#define STM32_IRQ_USART1_PRIORITY 12
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#define STM32_IRQ_USART2_PRIORITY 12
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#define STM32_IRQ_USART6_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_IRQ_PRIORITY 6
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM9 FALSE
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#define STM32_GPT_USE_TIM10 FALSE
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#define STM32_GPT_USE_TIM11 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 TRUE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_USE_I2C3 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 5
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#define STM32_I2C_I2C2_IRQ_PRIORITY 5
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#define STM32_I2C_I2C3_IRQ_PRIORITY 5
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_I2C3_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* I2S driver system settings.
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*/
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#define STM32_I2S_USE_SPI2 FALSE
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#define STM32_I2S_USE_SPI3 FALSE
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#define STM32_I2S_SPI2_IRQ_PRIORITY 10
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#define STM32_I2S_SPI3_IRQ_PRIORITY 10
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#define STM32_I2S_SPI2_DMA_PRIORITY 1
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#define STM32_I2S_SPI3_DMA_PRIORITY 1
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#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM9 FALSE
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#define STM32_ICU_USE_TIM10 FALSE
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#define STM32_ICU_USE_TIM11 FALSE
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM4 FALSE
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#define STM32_PWM_USE_TIM5 FALSE
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#define STM32_PWM_USE_TIM9 FALSE
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#define STM32_PWM_USE_TIM10 FALSE
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#define STM32_PWM_USE_TIM11 FALSE
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 TRUE
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#define STM32_SERIAL_USE_USART2 TRUE
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#define STM32_SERIAL_USE_USART6 FALSE
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_USE_SPI3 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 8
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#define STM32_ST_USE_TIMER 2
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USE_USART6 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_USART6_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define STM32_USB_USE_OTG1 TRUE
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#define STM32_USB_OTG1_IRQ_PRIORITY 14
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#define STM32_USB_OTG1_RX_FIFO_SIZE 512
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#define STM32_USB_HOST_WAKEUP_DURATION 2
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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#endif /* MCUCONF_H */
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@ -0,0 +1,57 @@
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// Copyright 2022 Mega Mind (@megamind4089)
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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|
||||
// Pindefs for v2.0.0
|
||||
// https://megamind4089.github.io/STeMCell/pinout/
|
||||
|
||||
// Left side (front)
|
||||
#ifdef STEMCELL_UART_SWAP
|
||||
# define D3 PAL_LINE(GPIOA, 3)
|
||||
# define D2 PAL_LINE(GPIOA, 2)
|
||||
#else
|
||||
# define D3 PAL_LINE(GPIOA, 2)
|
||||
# define D2 PAL_LINE(GPIOA, 3)
|
||||
#endif
|
||||
// GND
|
||||
// GND
|
||||
#ifdef STEMCELL_I2C_SWAP
|
||||
# define D1 PAL_LINE(GPIOB, 6)
|
||||
# define D0 PAL_LINE(GPIOB, 7)
|
||||
#else
|
||||
# define D1 PAL_LINE(GPIOB, 7)
|
||||
# define D0 PAL_LINE(GPIOB, 6)
|
||||
#endif
|
||||
|
||||
#define D4 PAL_LINE(GPIOA, 15)
|
||||
#define C6 PAL_LINE(GPIOB, 3)
|
||||
#define D7 PAL_LINE(GPIOB, 4)
|
||||
#define E6 PAL_LINE(GPIOB, 5)
|
||||
#define B4 PAL_LINE(GPIOB, 8)
|
||||
#define B5 PAL_LINE(GPIOB, 9)
|
||||
|
||||
// Right side (front)
|
||||
// RAW
|
||||
// GND
|
||||
// RESET
|
||||
// VCC
|
||||
#define F4 PAL_LINE(GPIOB, 10)
|
||||
#define F5 PAL_LINE(GPIOB, 2)
|
||||
#define F6 PAL_LINE(GPIOB, 1)
|
||||
#define F7 PAL_LINE(GPIOB, 0)
|
||||
|
||||
#define B1 PAL_LINE(GPIOA, 5)
|
||||
#define B3 PAL_LINE(GPIOA, 6)
|
||||
#define B2 PAL_LINE(GPIOA, 7)
|
||||
#define B6 PAL_LINE(GPIOA, 4)
|
||||
|
||||
// Extra elite-c compatible pinout
|
||||
#define B7 PAL_LINE(GPIOC, 13)
|
||||
#define D5 PAL_LINE(GPIOC, 14)
|
||||
#define C7 PAL_LINE(GPIOC, 15)
|
||||
#define F1 PAL_LINE(GPIOA, 0)
|
||||
#define F0 PAL_LINE(GPIOA, 1)
|
||||
|
||||
// TX/RX pins of promicro
|
||||
#define B0 PAL_LINE(GPIOA, 9) // unconnected pin
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
# Copyright 2022 Mega Mind (@megamind4089)
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
MCU := STM32F411
|
||||
BOARD := STEMCELL
|
||||
BOOTLOADER := tinyuf2
|
||||
|
||||
SERIAL_DRIVER ?= usart
|
||||
WS2812_DRIVER ?= bitbang
|
||||
|
||||
EEPROM_DRIVER = wear_leveling
|
||||
WEAR_LEVELING_DRIVER = legacy
|
||||
|
||||
|
||||
ifeq ($(strip $(STMC_US)), yes)
|
||||
OPT_DEFS += -DSTEMCELL_UART_SWAP
|
||||
endif
|
||||
|
||||
ifeq ($(strip $(STMC_IS)), yes)
|
||||
OPT_DEFS += -DSTEMCELL_I2C_SWAP
|
||||
endif
|
||||
|
||||
Loading…
Reference in New Issue