Merge remote-tracking branch 'origin/master' into develop
QMK Bot
commit
ceab485e58
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@ -39,126 +39,7 @@
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* SOFTWARE.
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*/
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#define SMC_PMSTAT_RUN ((uint8_t)0x01)
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#define SMC_PMSTAT_HSRUN ((uint8_t)0x80)
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#define F_CPU KINETIS_SYSCLK_FREQUENCY
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static inline int kinetis_hsrun_disable(void) {
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#if defined(MK66F18)
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if (SMC->PMSTAT == SMC_PMSTAT_HSRUN) {
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// First, reduce the CPU clock speed, but do not change
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// the peripheral speed (F_BUS). Serial1 & Serial2 baud
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// rates will be impacted, but most other peripherals
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// will continue functioning at the same speed.
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# if F_CPU == 256000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // TODO: TEST
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# elif F_CPU == 256000000 && F_BUS == 128000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // TODO: TEST
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# elif F_CPU == 240000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok
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# elif F_CPU == 240000000 && F_BUS == 80000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 240000000 && F_BUS == 120000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 216000000 && F_BUS == 54000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok
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# elif F_CPU == 216000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 216000000 && F_BUS == 108000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 192000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 3, 1, 7); // ok
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# elif F_CPU == 192000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 192000000 && F_BUS == 96000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 180000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 8); // ok
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# elif F_CPU == 180000000 && F_BUS == 90000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 7); // ok
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# elif F_CPU == 168000000 && F_BUS == 56000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 5); // ok
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# elif F_CPU == 144000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(2, 2, 2, 5); // ok
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# elif F_CPU == 144000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(1, 1, 1, 5); // ok
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# elif F_CPU == 120000000 && F_BUS == 60000000
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2 - 1) |
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# if defined(MK66F18)
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SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3 - 1) |
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# endif
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SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
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# else
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return 0;
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# endif
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// Then turn off HSRUN mode
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SMC->PMCTRL = SMC_PMCTRL_RUNM_SET(0);
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while (SMC->PMSTAT == SMC_PMSTAT_HSRUN)
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; // wait
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return 1;
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}
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#endif
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return 0;
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}
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static inline int kinetis_hsrun_enable(void) {
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#if defined(MK66F18)
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if (SMC->PMSTAT == SMC_PMSTAT_RUN) {
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// Turn HSRUN mode on
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SMC->PMCTRL = SMC_PMCTRL_RUNM_SET(3);
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while (SMC->PMSTAT != SMC_PMSTAT_HSRUN) {
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;
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} // wait
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// Then configure clock for full speed
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# if F_CPU == 256000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7);
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# elif F_CPU == 256000000 && F_BUS == 128000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7);
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# elif F_CPU == 240000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7);
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# elif F_CPU == 240000000 && F_BUS == 80000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 7);
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# elif F_CPU == 240000000 && F_BUS == 120000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7);
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# elif F_CPU == 216000000 && F_BUS == 54000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 7);
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# elif F_CPU == 216000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 7);
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# elif F_CPU == 216000000 && F_BUS == 108000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 7);
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# elif F_CPU == 192000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 3, 0, 6);
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# elif F_CPU == 192000000 && F_BUS == 64000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 6);
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# elif F_CPU == 192000000 && F_BUS == 96000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 6);
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# elif F_CPU == 180000000 && F_BUS == 60000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 6);
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# elif F_CPU == 180000000 && F_BUS == 90000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 6);
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# elif F_CPU == 168000000 && F_BUS == 56000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 5);
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# elif F_CPU == 144000000 && F_BUS == 48000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 2, 0, 4);
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# elif F_CPU == 144000000 && F_BUS == 72000000
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIVS(0, 1, 0, 4);
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# elif F_CPU == 120000000 && F_BUS == 60000000
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) | SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2 - 1) |
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# if defined(MK66F18)
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SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3 - 1) |
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# endif
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SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
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# else
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return 0;
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# endif
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return 1;
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}
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#endif
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return 0;
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}
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#if defined(K20x) || defined(MK66F18) /* chip selection */
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#if defined(K20x) /* chip selection */
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/* Teensy 3.0, 3.1, 3.2; mchck; infinity keyboard */
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// The EEPROM is really RAM with a hardware-based backup system to
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@ -188,34 +69,22 @@ static inline int kinetis_hsrun_enable(void) {
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//
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# define HANDLE_UNALIGNED_WRITES
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# if defined(K20x)
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# define EEPROM_MAX 2048
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# define EEPARTITION 0x03 // all 32K dataflash for EEPROM, none for Data
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# define EEESPLIT 0x30 // must be 0x30 on these chips
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# elif defined(MK66F18)
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# define EEPROM_MAX 4096
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# define EEPARTITION 0x05 // 128K dataflash for EEPROM, 128K for Data
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# define EEESPLIT 0x10 // best endurance: 0x00 = first 12%, 0x10 = first 25%, 0x30 = all equal
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# endif
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// Minimum EEPROM Endurance
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// ------------------------
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# if (EEPROM_SIZE == 4096)
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# define EEESIZE 0x02
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# elif (EEPROM_SIZE == 2048) // 35000 writes/byte or 70000 writes/word
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# define EEESIZE 0x03
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# if (EEPROM_SIZE == 2048) // 35000 writes/byte or 70000 writes/word
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# define EEESIZE 0x33
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# elif (EEPROM_SIZE == 1024) // 75000 writes/byte or 150000 writes/word
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# define EEESIZE 0x04
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# define EEESIZE 0x34
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# elif (EEPROM_SIZE == 512) // 155000 writes/byte or 310000 writes/word
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# define EEESIZE 0x05
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# define EEESIZE 0x35
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# elif (EEPROM_SIZE == 256) // 315000 writes/byte or 630000 writes/word
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# define EEESIZE 0x06
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# define EEESIZE 0x36
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# elif (EEPROM_SIZE == 128) // 635000 writes/byte or 1270000 writes/word
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# define EEESIZE 0x07
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# define EEESIZE 0x37
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# elif (EEPROM_SIZE == 64) // 1275000 writes/byte or 2550000 writes/word
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# define EEESIZE 0x08
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# define EEESIZE 0x38
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# elif (EEPROM_SIZE == 32) // 2555000 writes/byte or 5110000 writes/word
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# define EEESIZE 0x09
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# define EEESIZE 0x39
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# endif
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/** \brief eeprom initialization
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@ -228,21 +97,15 @@ void eeprom_initialize(void) {
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uint8_t status;
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if (FTFL->FCNFG & FTFL_FCNFG_RAMRDY) {
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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// FlexRAM is configured as traditional RAM
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// We need to reconfigure for EEPROM usage
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kinetis_hsrun_disable();
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FTFL->FCCOB0 = 0x80; // PGMPART = Program Partition Command
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FTFL->FCCOB3 = 0;
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FTFL->FCCOB4 = EEESPLIT | EEESIZE;
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FTFL->FCCOB5 = EEPARTITION;
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FTFL->FCCOB0 = 0x80; // PGMPART = Program Partition Command
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FTFL->FCCOB4 = EEESIZE; // EEPROM Size
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FTFL->FCCOB5 = 0x03; // 0K for Dataflash, 32K for EEPROM backup
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__disable_irq();
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// do_flash_cmd() must execute from RAM. Luckily the C syntax is simple...
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(*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFL->FSTAT));
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__enable_irq();
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kinetis_hsrun_enable();
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status = FTFL->FSTAT;
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if (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL)) {
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FTFL->FSTAT = (status & (FTFL_FSTAT_RDCOLERR | FTFL_FSTAT_ACCERR | FTFL_FSTAT_FPVIOL));
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@ -251,11 +114,11 @@ void eeprom_initialize(void) {
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}
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// wait for eeprom to become ready (is this really necessary?)
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while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) {
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if (++count > 200000) break;
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if (++count > 20000) break;
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}
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}
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# define FlexRAM ((volatile uint8_t *)0x14000000)
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# define FlexRAM ((uint8_t *)0x14000000)
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/** \brief eeprom read byte
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*
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@ -332,12 +195,8 @@ void eeprom_write_byte(uint8_t *addr, uint8_t value) {
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if (offset >= EEPROM_SIZE) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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@ -354,30 +213,18 @@ void eeprom_write_word(uint16_t *addr, uint16_t value) {
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if ((offset & 1) == 0) {
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# endif
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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# ifdef HANDLE_UNALIGNED_WRITES
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} else {
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (FlexRAM[offset + 1] != (value >> 8)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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FlexRAM[offset + 1] = value >> 8;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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# endif
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@ -397,57 +244,33 @@ void eeprom_write_dword(uint32_t *addr, uint32_t value) {
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case 0:
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# endif
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if (*(uint32_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint32_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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return;
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# ifdef HANDLE_UNALIGNED_WRITES
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case 2:
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (*(uint16_t *)(&FlexRAM[offset + 2]) != (value >> 16)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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return;
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default:
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if (FlexRAM[offset] != value) {
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kinetis_hsrun_disable();
|
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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FlexRAM[offset] = value;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (*(uint16_t *)(&FlexRAM[offset + 1]) != (value >> 8)) {
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kinetis_hsrun_disable();
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uint8_t stat = FTFL->FSTAT & 0x70;
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if (stat) FTFL->FSTAT = stat;
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*(uint16_t *)(&FlexRAM[offset + 1]) = value >> 8;
|
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flexram_wait();
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kinetis_hsrun_enable();
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}
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if (FlexRAM[offset + 3] != (value >> 24)) {
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kinetis_hsrun_disable();
|
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uint8_t stat = FTFL->FSTAT & 0x70;
|
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if (stat) FTFL->FSTAT = stat;
|
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FlexRAM[offset + 3] = value >> 24;
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flexram_wait();
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kinetis_hsrun_enable();
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}
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}
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# endif
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@ -465,7 +288,6 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
|
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
|
||||
if (len >= EEPROM_SIZE) len = EEPROM_SIZE;
|
||||
if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset;
|
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kinetis_hsrun_disable();
|
||||
while (len > 0) {
|
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uint32_t lsb = offset & 3;
|
||||
if (lsb == 0 && len >= 4) {
|
||||
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|
@ -476,8 +298,6 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
|
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val32 |= (*src++ << 16);
|
||||
val32 |= (*src++ << 24);
|
||||
if (*(uint32_t *)(&FlexRAM[offset]) != val32) {
|
||||
uint8_t stat = FTFL->FSTAT & 0x70;
|
||||
if (stat) FTFL->FSTAT = stat;
|
||||
*(uint32_t *)(&FlexRAM[offset]) = val32;
|
||||
flexram_wait();
|
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}
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||||
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|
@ -489,8 +309,6 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
|
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val16 = *src++;
|
||||
val16 |= (*src++ << 8);
|
||||
if (*(uint16_t *)(&FlexRAM[offset]) != val16) {
|
||||
uint8_t stat = FTFL->FSTAT & 0x70;
|
||||
if (stat) FTFL->FSTAT = stat;
|
||||
*(uint16_t *)(&FlexRAM[offset]) = val16;
|
||||
flexram_wait();
|
||||
}
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||||
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@ -500,8 +318,6 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
|
|||
// write 8 bits
|
||||
uint8_t val8 = *src++;
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||||
if (FlexRAM[offset] != val8) {
|
||||
uint8_t stat = FTFL->FSTAT & 0x70;
|
||||
if (stat) FTFL->FSTAT = stat;
|
||||
FlexRAM[offset] = val8;
|
||||
flexram_wait();
|
||||
}
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||||
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|
@ -509,7 +325,6 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
|
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len--;
|
||||
}
|
||||
}
|
||||
kinetis_hsrun_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
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