Update clock frequencies to match the infinity ergodox
parent
a702f4631e
commit
49a00a535f
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@ -29,21 +29,10 @@
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/* PEE mode - 48MHz system clock driven by external crystal. */
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
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#define KINETIS_PLLCLK_FREQUENCY 96000000UL
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#define KINETIS_SYSCLK_FREQUENCY 48000000UL
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#if 0
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/* FEI mode - 48 MHz with internal 32.768 kHz crystal */
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
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#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
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#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
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#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
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#define KINETIS_CLKDIV1_OUTDIV1 1
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#define KINETIS_CLKDIV1_OUTDIV2 1
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#define KINETIS_CLKDIV1_OUTDIV4 2
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#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
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#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
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#endif
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#define KINETIS_PLLCLK_FREQUENCY 72000000UL
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#define KINETIS_SYSCLK_FREQUENCY 72000000UL
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#define KINETIS_BUSCLK_FREQUENCY 36000000UL
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#define KINETIS_FLASHCLK_FREQUENCY 24000000UL
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/*
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* SERIAL driver system settings.
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