Stabilize Half-duplex PIO split comms (#17612)
parent
35d78aa8a4
commit
0348071810
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@ -142,6 +142,7 @@ void pio_serve_interrupt(void) {
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// the generated low level with 360mV will generate a logical zero.
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// the generated low level with 360mV will generate a logical zero.
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static inline void enter_rx_state(void) {
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static inline void enter_rx_state(void) {
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osalSysLock();
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osalSysLock();
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nvicEnableVector(RP_USBCTRL_IRQ_NUMBER, RP_IRQ_USB0_PRIORITY);
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// Wait for the transmitting state machines FIFO to run empty. At this point
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// Wait for the transmitting state machines FIFO to run empty. At this point
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// the last byte has been pulled from the transmitting state machines FIFO
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// the last byte has been pulled from the transmitting state machines FIFO
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// into the output shift register. We have to wait a tiny bit more until
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// into the output shift register. We have to wait a tiny bit more until
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@ -163,6 +164,9 @@ static inline void enter_rx_state(void) {
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static inline void leave_rx_state(void) {
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static inline void leave_rx_state(void) {
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osalSysLock();
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osalSysLock();
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// We don't want to be interrupted by frequent (1KHz) USB interrupts while
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// doing our timing critical sending operation.
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nvicDisableVector(RP_USBCTRL_IRQ_NUMBER);
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// In Half-duplex operation the tx pin dual-functions as sender and
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// In Half-duplex operation the tx pin dual-functions as sender and
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// receiver. To not receive the data we will send, we disable the receiving
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// receiver. To not receive the data we will send, we disable the receiving
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// state machine.
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// state machine.
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@ -194,12 +198,21 @@ static inline msg_t sync_tx(sysinterval_t timeout) {
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msg_t msg = MSG_OK;
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msg_t msg = MSG_OK;
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osalSysLock();
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osalSysLock();
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while (pio_sm_is_tx_fifo_full(pio, tx_state_machine)) {
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while (pio_sm_is_tx_fifo_full(pio, tx_state_machine)) {
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#if !defined(SERIAL_USART_FULL_DUPLEX)
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// Enable USB interrupts again, because we might sleep for a long time
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// here and don't want to be disconnected from the host.
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nvicEnableVector(RP_USBCTRL_IRQ_NUMBER, RP_IRQ_USB0_PRIORITY);
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#endif
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pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, true);
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pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, true);
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msg = osalThreadSuspendTimeoutS(&tx_thread, timeout);
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msg = osalThreadSuspendTimeoutS(&tx_thread, timeout);
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if (msg < MSG_OK) {
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if (msg < MSG_OK) {
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break;
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break;
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}
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}
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}
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}
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#if !defined(SERIAL_USART_FULL_DUPLEX)
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// Entering timing critical territory again.
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nvicDisableVector(RP_USBCTRL_IRQ_NUMBER);
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#endif
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osalSysUnlock();
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osalSysUnlock();
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return msg;
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return msg;
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}
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}
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@ -412,11 +425,12 @@ static inline void pio_init(pin_t tx_pin, pin_t rx_pin) {
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pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, true);
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pio_set_irq0_source_enabled(pio, pis_sm0_tx_fifo_not_full + tx_state_machine, true);
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pio_set_irq0_source_enabled(pio, pis_interrupt0, true);
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pio_set_irq0_source_enabled(pio, pis_interrupt0, true);
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// Enable PIO specific interrupt vector
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// Enable PIO specific interrupt vector, as the pio implementation is timing
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// critical we use the highest possible priority.
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#if defined(SERIAL_PIO_USE_PIO1)
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#if defined(SERIAL_PIO_USE_PIO1)
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nvicEnableVector(RP_PIO1_IRQ_0_NUMBER, RP_IRQ_UART0_PRIORITY);
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nvicEnableVector(RP_PIO1_IRQ_0_NUMBER, CORTEX_MAX_KERNEL_PRIORITY);
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#else
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#else
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nvicEnableVector(RP_PIO0_IRQ_0_NUMBER, RP_IRQ_UART0_PRIORITY);
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nvicEnableVector(RP_PIO0_IRQ_0_NUMBER, CORTEX_MAX_KERNEL_PRIORITY);
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#endif
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#endif
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enter_rx_state();
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enter_rx_state();
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