2022-06-17 22:06:44 +02:00
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// Copyright 2021 QMK
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// SPDX-License-Identifier: GPL-2.0-or-later
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2021-05-27 05:37:54 +02:00
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#pragma once
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#include "serial.h"
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#include <hal.h>
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2022-06-18 00:04:17 +02:00
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#if defined(SOFT_SERIAL_PIN)
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# define SERIAL_USART_TX_PIN SOFT_SERIAL_PIN
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#endif
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#if !defined(SERIAL_USART_TX_PIN)
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# define SERIAL_USART_TX_PIN A9
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#endif
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#if !defined(SERIAL_USART_RX_PIN)
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# define SERIAL_USART_RX_PIN A10
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#endif
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#if !defined(SELECT_SOFT_SERIAL_SPEED)
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# define SELECT_SOFT_SERIAL_SPEED 1
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#endif
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#if defined(SERIAL_USART_SPEED)
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// Allow advanced users to directly set SERIAL_USART_SPEED
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#elif SELECT_SOFT_SERIAL_SPEED == 0
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# define SERIAL_USART_SPEED 460800
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#elif SELECT_SOFT_SERIAL_SPEED == 1
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# define SERIAL_USART_SPEED 230400
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#elif SELECT_SOFT_SERIAL_SPEED == 2
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# define SERIAL_USART_SPEED 115200
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#elif SELECT_SOFT_SERIAL_SPEED == 3
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# define SERIAL_USART_SPEED 57600
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#elif SELECT_SOFT_SERIAL_SPEED == 4
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# define SERIAL_USART_SPEED 38400
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#elif SELECT_SOFT_SERIAL_SPEED == 5
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# define SERIAL_USART_SPEED 19200
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#else
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# error invalid SELECT_SOFT_SERIAL_SPEED value
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#endif
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#if !defined(SERIAL_USART_TIMEOUT)
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# define SERIAL_USART_TIMEOUT 20
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#endif
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2022-06-17 22:06:44 +02:00
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#if HAL_USE_SERIAL
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typedef SerialDriver QMKSerialDriver;
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typedef SerialConfig QMKSerialConfig;
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# if !defined(SERIAL_USART_DRIVER)
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# define SERIAL_USART_DRIVER SD1
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# endif
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#elif HAL_USE_SIO
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typedef SIODriver QMKSerialDriver;
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typedef SIOConfig QMKSerialConfig;
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# if !defined(SERIAL_USART_DRIVER)
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# define SERIAL_USART_DRIVER SIOD1
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# endif
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2021-07-02 00:24:08 +02:00
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#endif
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#if !defined(USE_GPIOV1)
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/* The default PAL alternate modes are used to signal that the pins are used for USART. */
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# if !defined(SERIAL_USART_TX_PAL_MODE)
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# define SERIAL_USART_TX_PAL_MODE 7
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# endif
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# if !defined(SERIAL_USART_RX_PAL_MODE)
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# define SERIAL_USART_RX_PAL_MODE 7
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# endif
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#endif
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#if !defined(USART_CR1_M0)
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2022-02-12 19:29:31 +01:00
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# define USART_CR1_M0 USART_CR1_M // some platforms (f1xx) dont have this so
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2021-05-27 05:37:54 +02:00
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#endif
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2021-07-02 00:24:08 +02:00
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#if !defined(SERIAL_USART_CR1)
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2022-02-12 19:29:31 +01:00
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# define SERIAL_USART_CR1 (USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0) // parity enable, odd parity, 9 bit length
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2021-05-27 05:37:54 +02:00
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#endif
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2021-07-02 00:24:08 +02:00
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#if !defined(SERIAL_USART_CR2)
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2022-02-12 19:29:31 +01:00
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# define SERIAL_USART_CR2 (USART_CR2_STOP_1) // 2 stop bits
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2021-05-27 05:37:54 +02:00
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#endif
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2021-07-02 00:24:08 +02:00
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#if !defined(SERIAL_USART_CR3)
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2021-05-27 05:37:54 +02:00
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# define SERIAL_USART_CR3 0
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#endif
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#if defined(USART1_REMAP)
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2021-05-29 22:53:10 +02:00
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# define USART_REMAP \
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do { \
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(AFIO->MAPR |= AFIO_MAPR_USART1_REMAP); \
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} while (0)
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2021-05-27 05:37:54 +02:00
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#elif defined(USART2_REMAP)
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2021-05-29 22:53:10 +02:00
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# define USART_REMAP \
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do { \
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(AFIO->MAPR |= AFIO_MAPR_USART2_REMAP); \
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} while (0)
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2021-05-27 05:37:54 +02:00
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#elif defined(USART3_PARTIALREMAP)
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2021-05-29 22:53:10 +02:00
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# define USART_REMAP \
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do { \
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(AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
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} while (0)
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2021-05-27 05:37:54 +02:00
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#elif defined(USART3_FULLREMAP)
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2021-05-29 22:53:10 +02:00
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# define USART_REMAP \
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do { \
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(AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP); \
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} while (0)
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2021-05-27 05:37:54 +02:00
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#endif
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