ibm4704_usb: Fix interrupt of clock(rising edge)
parent
6014d1014e
commit
9a2282157f
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@ -51,8 +51,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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#define IBM4704_DATA_DDR DDRD
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#define IBM4704_DATA_BIT 0
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/* Pin interrupt on rising edge */
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#define IBM4704_INT_INIT() do { EICRA |= ((1<<ISC11)|(0<<ISC10)); } while (0)
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/* Pin interrupt on rising edge of clock */
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#define IBM4704_INT_INIT() do { EICRA |= ((1<<ISC11)|(1<<ISC10)); } while (0)
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#define IBM4704_INT_ON() do { EIMSK |= (1<<INT1); } while (0)
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#define IBM4704_INT_OFF() do { EIMSK &= ~(1<<INT1); } while (0)
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#define IBM4704_INT_VECT INT1_vect
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@ -57,15 +57,15 @@ Keyboard to Host
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----------------
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Data bits are LSB first and Pairty is odd. Clock has around 60us high and 30us low part.
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____ __ __ __ __ __ __ __ __ __ ________
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Clock \____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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____ __ __ __ __ __ __ __ __ __ _______
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Clock \_____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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____ ____ ____ ____ ____ ____ ____ ____ ____ ____
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Data ____/ X____X____X____X____X____X____X____X____X____X________
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Start 0 1 2 3 4 5 6 7 P Stop
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Start bit: can be long as 300-350us.
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Inhibit: Pull Data line down to inhibit keyboard to send.
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Timing: Host reads bit while Clock is hi.
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Timing: Host reads bit while Clock is hi.(rising edge)
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Stop bit: Keyboard pulls down Data line to lo after 9th clock.
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@ -104,22 +104,6 @@ uint8_t ibm4704_recv_response(void)
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return rbuf_dequeue();
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}
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/*
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Keyboard to Host
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----------------
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Data bits are LSB first and Parity is odd. Clock has around 60us high and 30us low part.
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____ __ __ __ __ __ __ __ __ __ ________
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Clock \____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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____ ____ ____ ____ ____ ____ ____ ____ ____ ____
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Data ____/ X____X____X____X____X____X____X____X____X____X________
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Start 0 1 2 3 4 5 6 7 P Stop
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Start bit: can be long as 300-350us.
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Inhibit: Pull Data line down to inhibit keyboard to send.
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Timing: Host reads bit while Clock is hi.
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Stop bit: Keyboard pulls down Data line to lo after 9th clock.
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*/
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uint8_t ibm4704_recv(void)
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{
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if (rbuf_has_data()) {
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@ -129,25 +113,38 @@ uint8_t ibm4704_recv(void)
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}
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}
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/*
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Keyboard to Host
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----------------
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Data bits are LSB first and Parity is odd. Clock has around 60us high and 30us low part.
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____ __ __ __ __ __ __ __ __ __ _______
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Clock \_____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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____ ____ ____ ____ ____ ____ ____ ____ ____ ____
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Data ____/ X____X____X____X____X____X____X____X____X____X________
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Start 0 1 2 3 4 5 6 7 P Stop
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Start bit: can be long as 300-350us.
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Inhibit: Pull Data line down to inhibit keyboard to send.
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Timing: Host reads bit while Clock is hi.(rising edge)
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Stop bit: Keyboard pulls down Data line to lo after 9th clock.
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*/
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ISR(IBM4704_INT_VECT)
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{
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static enum {
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INIT, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY,
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} state = INIT;
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STOP, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY
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} state = STOP;
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// LSB first
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static uint8_t data = 0;
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// Odd parity
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static uint8_t parity = false;
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ibm4704_error = 0;
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// return unless falling edge
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if (clock_in()) { goto RETURN; } // why this occurs?
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state++;
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switch (state) {
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case START:
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switch (state++) {
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case STOP:
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// Data:Low
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WAIT(data_hi, 10, state);
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WAIT(data_lo, 10, state);
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break;
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case BIT0:
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case BIT1:
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@ -182,7 +179,7 @@ ERROR:
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while (ibm4704_send(0xFE)) _delay_ms(1); // resend
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xprintf("R:%02X%02X\n", state, data);
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DONE:
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state = INIT;
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state = STOP;
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data = 0;
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parity = false;
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RETURN:
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