60 lines
2.9 KiB
C
60 lines
2.9 KiB
C
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/**
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* \file
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*
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* \brief Instance description for PM
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*
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* Copyright (c) 2017 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_PM_INSTANCE_
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#define _SAMD51_PM_INSTANCE_
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/* ========== Register definition for PM peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PM_CTRLA (0x40000400) /**< \brief (PM) Control A */
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#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */
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#define REG_PM_INTENCLR (0x40000404) /**< \brief (PM) Interrupt Enable Clear */
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#define REG_PM_INTENSET (0x40000405) /**< \brief (PM) Interrupt Enable Set */
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#define REG_PM_INTFLAG (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */
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#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */
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#define REG_PM_HIBCFG (0x40000409) /**< \brief (PM) Hibernate Configuration */
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#define REG_PM_BKUPCFG (0x4000040A) /**< \brief (PM) Backup Configuration */
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#define REG_PM_PWSAKDLY (0x40000412) /**< \brief (PM) Power Switch Acknowledge Delay */
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#else
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#define REG_PM_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */
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#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */
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#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */
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#define REG_PM_INTENSET (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */
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#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */
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#define REG_PM_STDBYCFG (*(RwReg8 *)0x40000408UL) /**< \brief (PM) Standby Configuration */
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#define REG_PM_HIBCFG (*(RwReg8 *)0x40000409UL) /**< \brief (PM) Hibernate Configuration */
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#define REG_PM_BKUPCFG (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) Backup Configuration */
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#define REG_PM_PWSAKDLY (*(RwReg8 *)0x40000412UL) /**< \brief (PM) Power Switch Acknowledge Delay */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for PM peripheral ========== */
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#define PM_PD_NUM 0 // Number of switchable Power Domains
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#endif /* _SAMD51_PM_INSTANCE_ */
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