ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32 ESP32 8 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE Copyright 2022 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. Xtensa LX6 r0p0 little false true 3 false 32 32 0x00000000 0xFFFFFFFF AES AES (Advanced Encryption Standard) Accelerator AES 0x3FF01000 0x0 0x40 registers START 0x0 0x20 START Write 1 to start the AES operation. 0 1 write-only IDLE 0x4 0x20 IDLE AES Idle register. Reads ’zero’ while the AES Accelerator is busy processing; reads ’one’ otherwise. 0 1 read-only MODE 0x8 0x20 MODE Selects the AES accelerator mode of operation. See Table 22-1 for details. 0 8 read-write 8 0x4 KEY_%s 0x10 0x20 KEY AES key material register. 0 8 read-write 4 0x4 TEXT_%s 0x30 0x20 TEXT Plaintext and ciphertext register. 0 8 read-write ENDIAN 0x40 0x20 ENDIAN Endianness selection register. See Table 22-2 for details. 0 2 read-write APB_CTRL Advanced Peripheral Bus Controller APB_CTRL 0x3FF66000 0x0 0x44 registers SYSCLK_CONF 0x0 0x20 0x00002000 PRE_DIV_CNT 0 10 read-write CLK_320M_EN 10 1 read-write CLK_EN 11 1 read-write RST_TICK_CNT 12 1 read-write QUICK_CLK_CHNG 13 1 read-write XTAL_TICK_CONF 0x4 0x20 0x00000027 XTAL_TICK_NUM 0 8 read-write PLL_TICK_CONF 0x8 0x20 0x0000004F PLL_TICK_NUM 0 8 read-write CK8M_TICK_CONF 0xC 0x20 0x0000000B CK8M_TICK_NUM 0 8 read-write APB_SARADC_CTRL 0x10 0x20 0x007F8240 SARADC_START_FORCE 0 1 read-write SARADC_START 1 1 read-write SARADC_SAR2_MUX 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL 2 1 read-write SARADC_WORK_MODE 0: single mode 1: double mode 2: alternate mode 3 2 read-write SARADC_SAR_SEL 0: SAR1 1: SAR2 only work for single SAR mode 5 1 read-write SARADC_SAR_CLK_GATED 6 1 read-write SARADC_SAR_CLK_DIV SAR clock divider 7 8 read-write SARADC_SAR1_PATT_LEN 0 ~ 15 means length 1 ~ 16 15 4 read-write SARADC_SAR2_PATT_LEN 0 ~ 15 means length 1 ~ 16 19 4 read-write SARADC_SAR1_PATT_P_CLEAR clear the pointer of pattern table for DIG ADC1 CTRL 23 1 read-write SARADC_SAR2_PATT_P_CLEAR clear the pointer of pattern table for DIG ADC2 CTRL 24 1 read-write SARADC_DATA_SAR_SEL 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits. 25 1 read-write SARADC_DATA_TO_I2S 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix 26 1 read-write APB_SARADC_CTRL2 0x14 0x20 0x000001FE SARADC_MEAS_NUM_LIMIT 0 1 read-write SARADC_MAX_MEAS_NUM max conversion number 1 8 read-write SARADC_SAR1_INV 1: data to DIG ADC1 CTRL is inverted otherwise not 9 1 read-write SARADC_SAR2_INV 1: data to DIG ADC2 CTRL is inverted otherwise not 10 1 read-write APB_SARADC_FSM 0x18 0x20 0x0208FF08 SARADC_RSTB_WAIT 0 8 read-write SARADC_STANDBY_WAIT 8 8 read-write SARADC_START_WAIT 16 8 read-write SARADC_SAMPLE_CYCLE sample cycles 24 8 read-write APB_SARADC_SAR1_PATT_TAB1 0x1C 0x20 0x0F0F0F0F SARADC_SAR1_PATT_TAB1 item 0 ~ 3 for pattern table 1 (each item one byte) 0 32 read-write APB_SARADC_SAR1_PATT_TAB2 0x20 0x20 0x0F0F0F0F SARADC_SAR1_PATT_TAB2 Item 4 ~ 7 for pattern table 1 (each item one byte) 0 32 read-write APB_SARADC_SAR1_PATT_TAB3 0x24 0x20 0x0F0F0F0F SARADC_SAR1_PATT_TAB3 Item 8 ~ 11 for pattern table 1 (each item one byte) 0 32 read-write APB_SARADC_SAR1_PATT_TAB4 0x28 0x20 0x0F0F0F0F SARADC_SAR1_PATT_TAB4 Item 12 ~ 15 for pattern table 1 (each item one byte) 0 32 read-write APB_SARADC_SAR2_PATT_TAB1 0x2C 0x20 0x0F0F0F0F SARADC_SAR2_PATT_TAB1 item 0 ~ 3 for pattern table 2 (each item one byte) 0 32 read-write APB_SARADC_SAR2_PATT_TAB2 0x30 0x20 0x0F0F0F0F SARADC_SAR2_PATT_TAB2 Item 4 ~ 7 for pattern table 2 (each item one byte) 0 32 read-write APB_SARADC_SAR2_PATT_TAB3 0x34 0x20 0x0F0F0F0F SARADC_SAR2_PATT_TAB3 Item 8 ~ 11 for pattern table 2 (each item one byte) 0 32 read-write APB_SARADC_SAR2_PATT_TAB4 0x38 0x20 0x0F0F0F0F SARADC_SAR2_PATT_TAB4 Item 12 ~ 15 for pattern table 2 (each item one byte) 0 32 read-write APLL_TICK_CONF 0x3C 0x20 0x00000063 APLL_TICK_NUM 0 8 read-write DATE 0x7C 0x20 0x16042000 DATE 0 32 read-write BB Peripheral BB BB 0x3FF5D000 0x0 0x4 registers BBPD_CTRL Baseband control register 0x54 0x20 DC_EST_FORCE_PD 0 1 read-write DC_EST_FORCE_PU 1 1 read-write FFT_FORCE_PD 2 1 read-write FFT_FORCE_PU 3 1 read-write DPORT Peripheral DPORT DPORT 0x3FF00000 0x0 0x5C0 registers WIFI_MAC 0 WIFI_NMI 1 WIFI_BB 2 BT_MAC 3 BT_BB 4 BT_BB_NMI 5 RWBT 6 RWBLE 7 RWBT_NMI 8 RWBLE_NMI 9 PRO_BOOT_REMAP_CTRL 0x0 0x20 PRO_BOOT_REMAP 0 1 read-write APP_BOOT_REMAP_CTRL 0x4 0x20 APP_BOOT_REMAP 0 1 read-write ACCESS_CHECK 0x8 0x20 PRO 0 1 read-only APP 8 1 read-only PRO_DPORT_APB_MASK0 0xC 0x20 PRODPORT_APB_MASK0 0 32 read-write PRO_DPORT_APB_MASK1 0x10 0x20 PRODPORT_APB_MASK1 0 32 read-write APP_DPORT_APB_MASK0 0x14 0x20 APPDPORT_APB_MASK0 0 32 read-write APP_DPORT_APB_MASK1 0x18 0x20 APPDPORT_APB_MASK1 0 32 read-write PERI_CLK_EN 0x1C 0x20 PERI_CLK_EN 0 32 read-write PERI_RST_EN 0x20 0x20 PERI_RST_EN 0 32 read-write WIFI_BB_CFG 0x24 0x20 WIFI_BB_CFG 0 32 read-write WIFI_BB_CFG_2 0x28 0x20 WIFI_BB_CFG_2 0 32 read-write APPCPU_CTRL_A 0x2C 0x20 0x00000001 APPCPU_RESETTING 0 1 read-write APPCPU_CTRL_B 0x30 0x20 APPCPU_CLKGATE_EN 0 1 read-write APPCPU_CTRL_C 0x34 0x20 APPCPU_RUNSTALL 0 1 read-write APPCPU_CTRL_D 0x38 0x20 APPCPU_BOOT_ADDR 0 32 read-write CPU_PER_CONF 0x3C 0x20 CPUPERIOD_SEL 0 2 read-write LOWSPEED_CLK_SEL 2 1 read-write FAST_CLK_RTC_SEL 3 1 read-write PRO_CACHE_CTRL 0x40 0x20 0x00000010 PRO_CACHE_MODE 2 1 read-write PRO_CACHE_ENABLE 3 1 read-write PRO_CACHE_FLUSH_ENA 4 1 read-write PRO_CACHE_FLUSH_DONE 5 1 read-only PRO_CACHE_LOCK_0_EN 6 1 read-write PRO_CACHE_LOCK_1_EN 7 1 read-write PRO_CACHE_LOCK_2_EN 8 1 read-write PRO_CACHE_LOCK_3_EN 9 1 read-write PRO_SINGLE_IRAM_ENA 10 1 read-write PRO_DRAM_SPLIT 11 1 read-write PRO_AHB_SPI_REQ 12 1 read-only PRO_SLAVE_REQ 13 1 read-only AHB_SPI_REQ 14 1 read-only SLAVE_REQ 15 1 read-only PRO_DRAM_HL 16 1 read-write PRO_CACHE_CTRL1 0x44 0x20 0x000008FF PRO_CACHE_MASK_IRAM0 0 1 read-write PRO_CACHE_MASK_IRAM1 1 1 read-write PRO_CACHE_MASK_IROM0 2 1 read-write PRO_CACHE_MASK_DRAM1 3 1 read-write PRO_CACHE_MASK_DROM0 4 1 read-write PRO_CACHE_MASK_OPSDRAM 5 1 read-write PRO_CMMU_SRAM_PAGE_MODE 6 3 read-write PRO_CMMU_FLASH_PAGE_MODE 9 2 read-write PRO_CMMU_FORCE_ON 11 1 read-write PRO_CMMU_PD 12 1 read-write PRO_CACHE_MMU_IA_CLR 13 1 read-write PRO_CACHE_LOCK_0_ADDR 0x48 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write PRO_CACHE_LOCK_1_ADDR 0x4C 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write PRO_CACHE_LOCK_2_ADDR 0x50 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write PRO_CACHE_LOCK_3_ADDR 0x54 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write APP_CACHE_CTRL 0x58 0x20 0x00000010 APP_CACHE_MODE 2 1 read-write APP_CACHE_ENABLE 3 1 read-write APP_CACHE_FLUSH_ENA 4 1 read-write APP_CACHE_FLUSH_DONE 5 1 read-only APP_CACHE_LOCK_0_EN 6 1 read-write APP_CACHE_LOCK_1_EN 7 1 read-write APP_CACHE_LOCK_2_EN 8 1 read-write APP_CACHE_LOCK_3_EN 9 1 read-write APP_SINGLE_IRAM_ENA 10 1 read-write APP_DRAM_SPLIT 11 1 read-write APP_AHB_SPI_REQ 12 1 read-only APP_SLAVE_REQ 13 1 read-only APP_DRAM_HL 14 1 read-write APP_CACHE_CTRL1 0x5C 0x20 0x000008FF APP_CACHE_MASK_IRAM0 0 1 read-write APP_CACHE_MASK_IRAM1 1 1 read-write APP_CACHE_MASK_IROM0 2 1 read-write APP_CACHE_MASK_DRAM1 3 1 read-write APP_CACHE_MASK_DROM0 4 1 read-write APP_CACHE_MASK_OPSDRAM 5 1 read-write APP_CMMU_SRAM_PAGE_MODE 6 3 read-write APP_CMMU_FLASH_PAGE_MODE 9 2 read-write APP_CMMU_FORCE_ON 11 1 read-write APP_CMMU_PD 12 1 read-write APP_CACHE_MMU_IA_CLR 13 1 read-write APP_CACHE_LOCK_0_ADDR 0x60 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write APP_CACHE_LOCK_1_ADDR 0x64 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write APP_CACHE_LOCK_2_ADDR 0x68 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write APP_CACHE_LOCK_3_ADDR 0x6C 0x20 PRE 0 14 read-write MIN 14 4 read-write MAX 18 4 read-write TRACEMEM_MUX_MODE 0x70 0x20 TRACEMEM_MUX_MODE 0 2 read-write PRO_TRACEMEM_ENA 0x74 0x20 PRO_TRACEMEM_ENA 0 1 read-write APP_TRACEMEM_ENA 0x78 0x20 APP_TRACEMEM_ENA 0 1 read-write CACHE_MUX_MODE 0x7C 0x20 CACHE_MUX_MODE 0 2 read-write IMMU_PAGE_MODE 0x80 0x20 INTERNAL_SRAM_IMMU_ENA 0 1 read-write IMMU_PAGE_MODE 1 2 read-write DMMU_PAGE_MODE 0x84 0x20 INTERNAL_SRAM_DMMU_ENA 0 1 read-write DMMU_PAGE_MODE 1 2 read-write ROM_MPU_ENA 0x88 0x20 SHARE_ROM_MPU_ENA 0 1 read-write PRO_ROM_MPU_ENA 1 1 read-write APP_ROM_MPU_ENA 2 1 read-write MEM_PD_MASK 0x8C 0x20 0x00000001 LSLP_MEM_PD_MASK 0 1 read-write ROM_PD_CTRL 0x90 0x20 PRO_ROM_PD 0 1 read-write APP_ROM_PD 1 1 read-write SHARE_ROM_PD 2 6 read-write ROM_FO_CTRL 0x94 0x20 0x00000003 PRO_ROM_FO 0 1 read-write APP_ROM_FO 1 1 read-write SHARE_ROM_FO 2 6 read-write SRAM_PD_CTRL_0 0x98 0x20 SRAM_PD_0 0 32 read-write SRAM_PD_CTRL_1 0x9C 0x20 SRAM_PD_1 0 1 read-write SRAM_FO_CTRL_0 0xA0 0x20 0xFFFFFFFF SRAM_FO_0 0 32 read-write SRAM_FO_CTRL_1 0xA4 0x20 0x00000001 SRAM_FO_1 0 1 read-write IRAM_DRAM_AHB_SEL 0xA8 0x20 MASK_PRO_IRAM 0 1 read-write MASK_APP_IRAM 1 1 read-write MASK_PRO_DRAM 2 1 read-write MASK_APP_DRAM 3 1 read-write MASK_AHB 4 1 read-write MAC_DUMP_MODE 5 2 read-write TAG_FO_CTRL 0xAC 0x20 0x00000101 PRO_CACHE_TAG_FORCE_ON 0 1 read-write PRO_CACHE_TAG_PD 1 1 read-write APP_CACHE_TAG_FORCE_ON 8 1 read-write APP_CACHE_TAG_PD 9 1 read-write AHB_LITE_MASK 0xB0 0x20 PRO 0 1 read-write APP 4 1 read-write SDIO 8 1 read-write PRODPORT 9 1 read-write APPDPORT 10 1 read-write AHB_LITE_SDHOST_PID 11 3 read-write AHB_MPU_TABLE_0 0xB4 0x20 0xFFFFFFFF AHB_ACCESS_GRANT_0 0 32 read-write AHB_MPU_TABLE_1 0xB8 0x20 0x000001FF AHB_ACCESS_GRANT_1 0 9 read-write HOST_INF_SEL 0xBC 0x20 PERI_IO_SWAP 0 8 read-write LINK_DEVICE_SEL 8 8 read-write PERIP_CLK_EN 0xC0 0x20 0xF9C1E06F TIMERS_CLK_EN 0 1 read-write SPI01_CLK_EN 1 1 read-write UART_CLK_EN 2 1 read-write WDG_CLK_EN 3 1 read-write I2S0_CLK_EN 4 1 read-write UART1_CLK_EN 5 1 read-write SPI2_CLK_EN 6 1 read-write I2C0_EXT0_CLK_EN 7 1 read-write UHCI0_CLK_EN 8 1 read-write RMT_CLK_EN 9 1 read-write PCNT_CLK_EN 10 1 read-write LEDC_CLK_EN 11 1 read-write UHCI1_CLK_EN 12 1 read-write TIMERGROUP_CLK_EN 13 1 read-write EFUSE_CLK_EN 14 1 read-write TIMERGROUP1_CLK_EN 15 1 read-write SPI3_CLK_EN 16 1 read-write PWM0_CLK_EN 17 1 read-write I2C_EXT1_CLK_EN 18 1 read-write TWAI_CLK_EN 19 1 read-write PWM1_CLK_EN 20 1 read-write I2S1_CLK_EN 21 1 read-write SPI_DMA_CLK_EN 22 1 read-write UART2_CLK_EN 23 1 read-write UART_MEM_CLK_EN 24 1 read-write PWM2_CLK_EN 25 1 read-write PWM3_CLK_EN 26 1 read-write PERIP_RST_EN 0xC4 0x20 TIMERS_RST 0 1 read-write SPI01_RST 1 1 read-write UART_RST 2 1 read-write WDG_RST 3 1 read-write I2S0_RST 4 1 read-write UART1_RST 5 1 read-write SPI2_RST 6 1 read-write I2C0_EXT0_RST 7 1 read-write UHCI0_RST 8 1 read-write RMT_RST 9 1 read-write PCNT_RST 10 1 read-write LEDC_RST 11 1 read-write UHCI1_RST 12 1 read-write TIMERGROUP_RST 13 1 read-write EFUSE_RST 14 1 read-write TIMERGROUP1_RST 15 1 read-write SPI3_RST 16 1 read-write PWM0_RST 17 1 read-write I2C_EXT1_RST 18 1 read-write TWAI_RST 19 1 read-write PWM1_RST 20 1 read-write I2S1_RST 21 1 read-write SPI_DMA_RST 22 1 read-write UART2_RST 23 1 read-write UART_MEM_RST 24 1 read-write PWM2_RST 25 1 read-write PWM3_RST 26 1 read-write SLAVE_SPI_CONFIG 0xC8 0x20 SLAVE_SPI_MASK_PRO 0 1 read-write SLAVE_SPI_MASK_APP 4 1 read-write SPI_ENCRYPT_ENABLE 8 1 read-write SPI_DECRYPT_ENABLE 12 1 read-write WIFI_CLK_EN 0xCC 0x20 0xFFFCE030 WIFI_CLK_EN 0 32 read-write WIFI_CLK_WIFI_EN 0 3 read-write WIFI_CLK_WIFI_BT_COMMON 0 6 read-write WIFI_CLK_BT_EN 11 3 read-write CORE_RST_EN 0xD0 0x20 CORE_RST 0 8 read-write BB_RST 0 1 read-write FE_RST 1 1 read-write MAC_RST 2 1 read-write BT_RST 3 1 read-write BTMAC_RST 4 1 read-write SDIO_RST 5 1 read-write SDIO_HOST_RST 6 1 read-write EMAC_RST 7 1 read-write MACPWR_RST 8 1 read-write RW_BTMAC_RST 9 1 read-write RW_BTLP_RST 10 1 read-write BT_LPCK_DIV_INT 0xD4 0x20 0x000000FF BT_LPCK_DIV_NUM 0 12 read-write BTEXTWAKEUP_REQ 12 1 read-write BT_LPCK_DIV_FRAC 0xD8 0x20 0x02001001 BT_LPCK_DIV_B 0 12 read-write BT_LPCK_DIV_A 12 12 read-write LPCLK_SEL_RTC_SLOW 24 1 read-write LPCLK_SEL_8M 25 1 read-write LPCLK_SEL_XTAL 26 1 read-write LPCLK_SEL_XTAL32K 27 1 read-write CPU_INTR_FROM_CPU_0 0xDC 0x20 CPU_INTR_FROM_CPU_0 0 1 read-write CPU_INTR_FROM_CPU_1 0xE0 0x20 CPU_INTR_FROM_CPU_1 0 1 read-write CPU_INTR_FROM_CPU_2 0xE4 0x20 CPU_INTR_FROM_CPU_2 0 1 read-write CPU_INTR_FROM_CPU_3 0xE8 0x20 CPU_INTR_FROM_CPU_3 0 1 read-write PRO_INTR_STATUS_0 0xEC 0x20 PRO_INTR_STATUS_0 0 32 read-only PRO_INTR_STATUS_1 0xF0 0x20 PRO_INTR_STATUS_1 0 32 read-only PRO_INTR_STATUS_2 0xF4 0x20 PRO_INTR_STATUS_2 0 32 read-only APP_INTR_STATUS_0 0xF8 0x20 APP_INTR_STATUS_0 0 32 read-only APP_INTR_STATUS_1 0xFC 0x20 APP_INTR_STATUS_1 0 32 read-only APP_INTR_STATUS_2 0x100 0x20 APP_INTR_STATUS_2 0 32 read-only PRO_MAC_INTR_MAP 0x104 0x20 0x00000010 PRO_MAC_INTR_MAP 0 5 read-write PRO_MAC_NMI_MAP 0x108 0x20 0x00000010 PRO_MAC_NMI_MAP 0 5 read-write PRO_BB_INT_MAP 0x10C 0x20 0x00000010 PRO_BB_INT_MAP 0 5 read-write PRO_BT_MAC_INT_MAP 0x110 0x20 0x00000010 PRO_BT_MAC_INT_MAP 0 5 read-write PRO_BT_BB_INT_MAP 0x114 0x20 0x00000010 PRO_BT_BB_INT_MAP 0 5 read-write PRO_BT_BB_NMI_MAP 0x118 0x20 0x00000010 PRO_BT_BB_NMI_MAP 0 5 read-write PRO_RWBT_IRQ_MAP 0x11C 0x20 0x00000010 PRO_RWBT_IRQ_MAP 0 5 read-write PRO_RWBLE_IRQ_MAP 0x120 0x20 0x00000010 PRO_RWBLE_IRQ_MAP 0 5 read-write PRO_RWBT_NMI_MAP 0x124 0x20 0x00000010 PRO_RWBT_NMI_MAP 0 5 read-write PRO_RWBLE_NMI_MAP 0x128 0x20 0x00000010 PRO_RWBLE_NMI_MAP 0 5 read-write PRO_SLC0_INTR_MAP 0x12C 0x20 0x00000010 PRO_SLC0_INTR_MAP 0 5 read-write PRO_SLC1_INTR_MAP 0x130 0x20 0x00000010 PRO_SLC1_INTR_MAP 0 5 read-write PRO_UHCI0_INTR_MAP 0x134 0x20 0x00000010 PRO_UHCI0_INTR_MAP 0 5 read-write PRO_UHCI1_INTR_MAP 0x138 0x20 0x00000010 PRO_UHCI1_INTR_MAP 0 5 read-write PRO_TG_T0_LEVEL_INT_MAP 0x13C 0x20 0x00000010 PRO_TG_T0_LEVEL_INT_MAP 0 5 read-write PRO_TG_T1_LEVEL_INT_MAP 0x140 0x20 0x00000010 PRO_TG_T1_LEVEL_INT_MAP 0 5 read-write PRO_TG_WDT_LEVEL_INT_MAP 0x144 0x20 0x00000010 PRO_TG_WDT_LEVEL_INT_MAP 0 5 read-write PRO_TG_LACT_LEVEL_INT_MAP 0x148 0x20 0x00000010 PRO_TG_LACT_LEVEL_INT_MAP 0 5 read-write PRO_TG1_T0_LEVEL_INT_MAP 0x14C 0x20 0x00000010 PRO_TG1_T0_LEVEL_INT_MAP 0 5 read-write PRO_TG1_T1_LEVEL_INT_MAP 0x150 0x20 0x00000010 PRO_TG1_T1_LEVEL_INT_MAP 0 5 read-write PRO_TG1_WDT_LEVEL_INT_MAP 0x154 0x20 0x00000010 PRO_TG1_WDT_LEVEL_INT_MAP 0 5 read-write PRO_TG1_LACT_LEVEL_INT_MAP 0x158 0x20 0x00000010 PRO_TG1_LACT_LEVEL_INT_MAP 0 5 read-write PRO_GPIO_INTERRUPT_MAP 0x15C 0x20 0x00000010 PRO_GPIO_INTERRUPT_PRO_MAP 0 5 read-write PRO_GPIO_INTERRUPT_NMI_MAP 0x160 0x20 0x00000010 PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0 5 read-write PRO_CPU_INTR_FROM_CPU_0_MAP 0x164 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_0_MAP 0 5 read-write PRO_CPU_INTR_FROM_CPU_1_MAP 0x168 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_1_MAP 0 5 read-write PRO_CPU_INTR_FROM_CPU_2_MAP 0x16C 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_2_MAP 0 5 read-write PRO_CPU_INTR_FROM_CPU_3_MAP 0x170 0x20 0x00000010 PRO_CPU_INTR_FROM_CPU_3_MAP 0 5 read-write PRO_SPI_INTR_0_MAP 0x174 0x20 0x00000010 PRO_SPI_INTR_0_MAP 0 5 read-write PRO_SPI_INTR_1_MAP 0x178 0x20 0x00000010 PRO_SPI_INTR_1_MAP 0 5 read-write PRO_SPI_INTR_2_MAP 0x17C 0x20 0x00000010 PRO_SPI_INTR_2_MAP 0 5 read-write PRO_SPI_INTR_3_MAP 0x180 0x20 0x00000010 PRO_SPI_INTR_3_MAP 0 5 read-write PRO_I2S0_INT_MAP 0x184 0x20 0x00000010 PRO_I2S0_INT_MAP 0 5 read-write PRO_I2S1_INT_MAP 0x188 0x20 0x00000010 PRO_I2S1_INT_MAP 0 5 read-write PRO_UART_INTR_MAP 0x18C 0x20 0x00000010 PRO_UART_INTR_MAP 0 5 read-write PRO_UART1_INTR_MAP 0x190 0x20 0x00000010 PRO_UART1_INTR_MAP 0 5 read-write PRO_UART2_INTR_MAP 0x194 0x20 0x00000010 PRO_UART2_INTR_MAP 0 5 read-write PRO_SDIO_HOST_INTERRUPT_MAP 0x198 0x20 0x00000010 PRO_SDIO_HOST_INTERRUPT_MAP 0 5 read-write PRO_EMAC_INT_MAP 0x19C 0x20 0x00000010 PRO_EMAC_INT_MAP 0 5 read-write PRO_PWM0_INTR_MAP 0x1A0 0x20 0x00000010 PRO_PWM0_INTR_MAP 0 5 read-write PRO_PWM1_INTR_MAP 0x1A4 0x20 0x00000010 PRO_PWM1_INTR_MAP 0 5 read-write PRO_PWM2_INTR_MAP 0x1A8 0x20 0x00000010 PRO_PWM2_INTR_MAP 0 5 read-write PRO_PWM3_INTR_MAP 0x1AC 0x20 0x00000010 PRO_PWM3_INTR_MAP 0 5 read-write PRO_LEDC_INT_MAP 0x1B0 0x20 0x00000010 PRO_LEDC_INT_MAP 0 5 read-write PRO_EFUSE_INT_MAP 0x1B4 0x20 0x00000010 PRO_EFUSE_INT_MAP 0 5 read-write PRO_CAN_INT_MAP 0x1B8 0x20 0x00000010 PRO_CAN_INT_MAP 0 5 read-write PRO_RTC_CORE_INTR_MAP 0x1BC 0x20 0x00000010 PRO_RTC_CORE_INTR_MAP 0 5 read-write PRO_RMT_INTR_MAP 0x1C0 0x20 0x00000010 PRO_RMT_INTR_MAP 0 5 read-write PRO_PCNT_INTR_MAP 0x1C4 0x20 0x00000010 PRO_PCNT_INTR_MAP 0 5 read-write PRO_I2C_EXT0_INTR_MAP 0x1C8 0x20 0x00000010 PRO_I2C_EXT0_INTR_MAP 0 5 read-write PRO_I2C_EXT1_INTR_MAP 0x1CC 0x20 0x00000010 PRO_I2C_EXT1_INTR_MAP 0 5 read-write PRO_RSA_INTR_MAP 0x1D0 0x20 0x00000010 PRO_RSA_INTR_MAP 0 5 read-write PRO_SPI1_DMA_INT_MAP 0x1D4 0x20 0x00000010 PRO_SPI1_DMA_INT_MAP 0 5 read-write PRO_SPI2_DMA_INT_MAP 0x1D8 0x20 0x00000010 PRO_SPI2_DMA_INT_MAP 0 5 read-write PRO_SPI3_DMA_INT_MAP 0x1DC 0x20 0x00000010 PRO_SPI3_DMA_INT_MAP 0 5 read-write PRO_WDG_INT_MAP 0x1E0 0x20 0x00000010 PRO_WDG_INT_MAP 0 5 read-write PRO_TIMER_INT1_MAP 0x1E4 0x20 0x00000010 PRO_TIMER_INT1_MAP 0 5 read-write PRO_TIMER_INT2_MAP 0x1E8 0x20 0x00000010 PRO_TIMER_INT2_MAP 0 5 read-write PRO_TG_T0_EDGE_INT_MAP 0x1EC 0x20 0x00000010 PRO_TG_T0_EDGE_INT_MAP 0 5 read-write PRO_TG_T1_EDGE_INT_MAP 0x1F0 0x20 0x00000010 PRO_TG_T1_EDGE_INT_MAP 0 5 read-write PRO_TG_WDT_EDGE_INT_MAP 0x1F4 0x20 0x00000010 PRO_TG_WDT_EDGE_INT_MAP 0 5 read-write PRO_TG_LACT_EDGE_INT_MAP 0x1F8 0x20 0x00000010 PRO_TG_LACT_EDGE_INT_MAP 0 5 read-write PRO_TG1_T0_EDGE_INT_MAP 0x1FC 0x20 0x00000010 PRO_TG1_T0_EDGE_INT_MAP 0 5 read-write PRO_TG1_T1_EDGE_INT_MAP 0x200 0x20 0x00000010 PRO_TG1_T1_EDGE_INT_MAP 0 5 read-write PRO_TG1_WDT_EDGE_INT_MAP 0x204 0x20 0x00000010 PRO_TG1_WDT_EDGE_INT_MAP 0 5 read-write PRO_TG1_LACT_EDGE_INT_MAP 0x208 0x20 0x00000010 PRO_TG1_LACT_EDGE_INT_MAP 0 5 read-write PRO_MMU_IA_INT_MAP 0x20C 0x20 0x00000010 PRO_MMU_IA_INT_MAP 0 5 read-write PRO_MPU_IA_INT_MAP 0x210 0x20 0x00000010 PRO_MPU_IA_INT_MAP 0 5 read-write PRO_CACHE_IA_INT_MAP 0x214 0x20 0x00000010 PRO_CACHE_IA_INT_MAP 0 5 read-write APP_MAC_INTR_MAP 0x218 0x20 0x00000010 APP_MAC_INTR_MAP 0 5 read-write APP_MAC_NMI_MAP 0x21C 0x20 0x00000010 APP_MAC_NMI_MAP 0 5 read-write APP_BB_INT_MAP 0x220 0x20 0x00000010 APP_BB_INT_MAP 0 5 read-write APP_BT_MAC_INT_MAP 0x224 0x20 0x00000010 APP_BT_MAC_INT_MAP 0 5 read-write APP_BT_BB_INT_MAP 0x228 0x20 0x00000010 APP_BT_BB_INT_MAP 0 5 read-write APP_BT_BB_NMI_MAP 0x22C 0x20 0x00000010 APP_BT_BB_NMI_MAP 0 5 read-write APP_RWBT_IRQ_MAP 0x230 0x20 0x00000010 APP_RWBT_IRQ_MAP 0 5 read-write APP_RWBLE_IRQ_MAP 0x234 0x20 0x00000010 APP_RWBLE_IRQ_MAP 0 5 read-write APP_RWBT_NMI_MAP 0x238 0x20 0x00000010 APP_RWBT_NMI_MAP 0 5 read-write APP_RWBLE_NMI_MAP 0x23C 0x20 0x00000010 APP_RWBLE_NMI_MAP 0 5 read-write APP_SLC0_INTR_MAP 0x240 0x20 0x00000010 APP_SLC0_INTR_MAP 0 5 read-write APP_SLC1_INTR_MAP 0x244 0x20 0x00000010 APP_SLC1_INTR_MAP 0 5 read-write APP_UHCI0_INTR_MAP 0x248 0x20 0x00000010 APP_UHCI0_INTR_MAP 0 5 read-write APP_UHCI1_INTR_MAP 0x24C 0x20 0x00000010 APP_UHCI1_INTR_MAP 0 5 read-write APP_TG_T0_LEVEL_INT_MAP 0x250 0x20 0x00000010 APP_TG_T0_LEVEL_INT_MAP 0 5 read-write APP_TG_T1_LEVEL_INT_MAP 0x254 0x20 0x00000010 APP_TG_T1_LEVEL_INT_MAP 0 5 read-write APP_TG_WDT_LEVEL_INT_MAP 0x258 0x20 0x00000010 APP_TG_WDT_LEVEL_INT_MAP 0 5 read-write APP_TG_LACT_LEVEL_INT_MAP 0x25C 0x20 0x00000010 APP_TG_LACT_LEVEL_INT_MAP 0 5 read-write APP_TG1_T0_LEVEL_INT_MAP 0x260 0x20 0x00000010 APP_TG1_T0_LEVEL_INT_MAP 0 5 read-write APP_TG1_T1_LEVEL_INT_MAP 0x264 0x20 0x00000010 APP_TG1_T1_LEVEL_INT_MAP 0 5 read-write APP_TG1_WDT_LEVEL_INT_MAP 0x268 0x20 0x00000010 APP_TG1_WDT_LEVEL_INT_MAP 0 5 read-write APP_TG1_LACT_LEVEL_INT_MAP 0x26C 0x20 0x00000010 APP_TG1_LACT_LEVEL_INT_MAP 0 5 read-write APP_GPIO_INTERRUPT_MAP 0x270 0x20 0x00000010 APP_GPIO_INTERRUPT_APP_MAP 0 5 read-write APP_GPIO_INTERRUPT_NMI_MAP 0x274 0x20 0x00000010 APP_GPIO_INTERRUPT_APP_NMI_MAP 0 5 read-write APP_CPU_INTR_FROM_CPU_0_MAP 0x278 0x20 0x00000010 APP_CPU_INTR_FROM_CPU_0_MAP 0 5 read-write APP_CPU_INTR_FROM_CPU_1_MAP 0x27C 0x20 0x00000010 APP_CPU_INTR_FROM_CPU_1_MAP 0 5 read-write APP_CPU_INTR_FROM_CPU_2_MAP 0x280 0x20 0x00000010 APP_CPU_INTR_FROM_CPU_2_MAP 0 5 read-write APP_CPU_INTR_FROM_CPU_3_MAP 0x284 0x20 0x00000010 APP_CPU_INTR_FROM_CPU_3_MAP 0 5 read-write APP_SPI_INTR_0_MAP 0x288 0x20 0x00000010 APP_SPI_INTR_0_MAP 0 5 read-write APP_SPI_INTR_1_MAP 0x28C 0x20 0x00000010 APP_SPI_INTR_1_MAP 0 5 read-write APP_SPI_INTR_2_MAP 0x290 0x20 0x00000010 APP_SPI_INTR_2_MAP 0 5 read-write APP_SPI_INTR_3_MAP 0x294 0x20 0x00000010 APP_SPI_INTR_3_MAP 0 5 read-write APP_I2S0_INT_MAP 0x298 0x20 0x00000010 APP_I2S0_INT_MAP 0 5 read-write APP_I2S1_INT_MAP 0x29C 0x20 0x00000010 APP_I2S1_INT_MAP 0 5 read-write APP_UART_INTR_MAP 0x2A0 0x20 0x00000010 APP_UART_INTR_MAP 0 5 read-write APP_UART1_INTR_MAP 0x2A4 0x20 0x00000010 APP_UART1_INTR_MAP 0 5 read-write APP_UART2_INTR_MAP 0x2A8 0x20 0x00000010 APP_UART2_INTR_MAP 0 5 read-write APP_SDIO_HOST_INTERRUPT_MAP 0x2AC 0x20 0x00000010 APP_SDIO_HOST_INTERRUPT_MAP 0 5 read-write APP_EMAC_INT_MAP 0x2B0 0x20 0x00000010 APP_EMAC_INT_MAP 0 5 read-write APP_PWM0_INTR_MAP 0x2B4 0x20 0x00000010 APP_PWM0_INTR_MAP 0 5 read-write APP_PWM1_INTR_MAP 0x2B8 0x20 0x00000010 APP_PWM1_INTR_MAP 0 5 read-write APP_PWM2_INTR_MAP 0x2BC 0x20 0x00000010 APP_PWM2_INTR_MAP 0 5 read-write APP_PWM3_INTR_MAP 0x2C0 0x20 0x00000010 APP_PWM3_INTR_MAP 0 5 read-write APP_LEDC_INT_MAP 0x2C4 0x20 0x00000010 APP_LEDC_INT_MAP 0 5 read-write APP_EFUSE_INT_MAP 0x2C8 0x20 0x00000010 APP_EFUSE_INT_MAP 0 5 read-write APP_CAN_INT_MAP 0x2CC 0x20 0x00000010 APP_CAN_INT_MAP 0 5 read-write APP_RTC_CORE_INTR_MAP 0x2D0 0x20 0x00000010 APP_RTC_CORE_INTR_MAP 0 5 read-write APP_RMT_INTR_MAP 0x2D4 0x20 0x00000010 APP_RMT_INTR_MAP 0 5 read-write APP_PCNT_INTR_MAP 0x2D8 0x20 0x00000010 APP_PCNT_INTR_MAP 0 5 read-write APP_I2C_EXT0_INTR_MAP 0x2DC 0x20 0x00000010 APP_I2C_EXT0_INTR_MAP 0 5 read-write APP_I2C_EXT1_INTR_MAP 0x2E0 0x20 0x00000010 APP_I2C_EXT1_INTR_MAP 0 5 read-write APP_RSA_INTR_MAP 0x2E4 0x20 0x00000010 APP_RSA_INTR_MAP 0 5 read-write APP_SPI1_DMA_INT_MAP 0x2E8 0x20 0x00000010 APP_SPI1_DMA_INT_MAP 0 5 read-write APP_SPI2_DMA_INT_MAP 0x2EC 0x20 0x00000010 APP_SPI2_DMA_INT_MAP 0 5 read-write APP_SPI3_DMA_INT_MAP 0x2F0 0x20 0x00000010 APP_SPI3_DMA_INT_MAP 0 5 read-write APP_WDG_INT_MAP 0x2F4 0x20 0x00000010 APP_WDG_INT_MAP 0 5 read-write APP_TIMER_INT1_MAP 0x2F8 0x20 0x00000010 APP_TIMER_INT1_MAP 0 5 read-write APP_TIMER_INT2_MAP 0x2FC 0x20 0x00000010 APP_TIMER_INT2_MAP 0 5 read-write APP_TG_T0_EDGE_INT_MAP 0x300 0x20 0x00000010 APP_TG_T0_EDGE_INT_MAP 0 5 read-write APP_TG_T1_EDGE_INT_MAP 0x304 0x20 0x00000010 APP_TG_T1_EDGE_INT_MAP 0 5 read-write APP_TG_WDT_EDGE_INT_MAP 0x308 0x20 0x00000010 APP_TG_WDT_EDGE_INT_MAP 0 5 read-write APP_TG_LACT_EDGE_INT_MAP 0x30C 0x20 0x00000010 APP_TG_LACT_EDGE_INT_MAP 0 5 read-write APP_TG1_T0_EDGE_INT_MAP 0x310 0x20 0x00000010 APP_TG1_T0_EDGE_INT_MAP 0 5 read-write APP_TG1_T1_EDGE_INT_MAP 0x314 0x20 0x00000010 APP_TG1_T1_EDGE_INT_MAP 0 5 read-write APP_TG1_WDT_EDGE_INT_MAP 0x318 0x20 0x00000010 APP_TG1_WDT_EDGE_INT_MAP 0 5 read-write APP_TG1_LACT_EDGE_INT_MAP 0x31C 0x20 0x00000010 APP_TG1_LACT_EDGE_INT_MAP 0 5 read-write APP_MMU_IA_INT_MAP 0x320 0x20 0x00000010 APP_MMU_IA_INT_MAP 0 5 read-write APP_MPU_IA_INT_MAP 0x324 0x20 0x00000010 APP_MPU_IA_INT_MAP 0 5 read-write APP_CACHE_IA_INT_MAP 0x328 0x20 0x00000010 APP_CACHE_IA_INT_MAP 0 5 read-write AHBLITE_MPU_TABLE_UART 0x32C 0x20 UART_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SPI1 0x330 0x20 SPI1_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SPI0 0x334 0x20 SPI0_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_GPIO 0x338 0x20 GPIO_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_FE2 0x33C 0x20 FE2_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_FE 0x340 0x20 FE_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_TIMER 0x344 0x20 TIMER_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_RTC 0x348 0x20 RTC_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_IO_MUX 0x34C 0x20 IOMUX_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_WDG 0x350 0x20 WDG_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_HINF 0x354 0x20 HINF_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_UHCI1 0x358 0x20 UHCI1_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_MISC 0x35C 0x20 MISC_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_I2C 0x360 0x20 I2C_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_I2S0 0x364 0x20 I2S0_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_UART1 0x368 0x20 UART1_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_BT 0x36C 0x20 BT_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_BT_BUFFER 0x370 0x20 BTBUFFER_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_I2C_EXT0 0x374 0x20 I2CEXT0_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_UHCI0 0x378 0x20 UHCI0_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SLCHOST 0x37C 0x20 SLCHOST_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_RMT 0x380 0x20 RMT_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_PCNT 0x384 0x20 PCNT_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SLC 0x388 0x20 SLC_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_LEDC 0x38C 0x20 LEDC_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_EFUSE 0x390 0x20 EFUSE_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SPI_ENCRYPT 0x394 0x20 SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_BB 0x398 0x20 BB_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_PWM0 0x39C 0x20 PWM0_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_TIMERGROUP 0x3A0 0x20 TIMERGROUP_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_TIMERGROUP1 0x3A4 0x20 TIMERGROUP1_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SPI2 0x3A8 0x20 SPI2_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SPI3 0x3AC 0x20 SPI3_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_APB_CTRL 0x3B0 0x20 APBCTRL_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_I2C_EXT1 0x3B4 0x20 I2CEXT1_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_SDIO_HOST 0x3B8 0x20 SDIOHOST_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_EMAC 0x3BC 0x20 EMAC_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_CAN 0x3C0 0x20 CAN_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_PWM1 0x3C4 0x20 PWM1_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_I2S1 0x3C8 0x20 I2S1_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_UART2 0x3CC 0x20 UART2_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_PWM2 0x3D0 0x20 PWM2_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_PWM3 0x3D4 0x20 PWM3_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_RWBT 0x3D8 0x20 RWBT_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_BTMAC 0x3DC 0x20 BTMAC_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_WIFIMAC 0x3E0 0x20 WIFIMAC_ACCESS_GRANT_CONFIG 0 6 read-write AHBLITE_MPU_TABLE_PWR 0x3E4 0x20 PWR_ACCESS_GRANT_CONFIG 0 6 read-write MEM_ACCESS_DBUG0 0x3E8 0x20 PRO_ROM_MPU_AD 0 1 read-only PRO_ROM_IA 1 1 read-only APP_ROM_MPU_AD 2 1 read-only APP_ROM_IA 3 1 read-only SHARE_ROM_MPU_AD 4 2 read-only SHARE_ROM_IA 6 4 read-only INTERNAL_SRAM_MMU_AD 10 4 read-only INTERNAL_SRAM_IA 14 12 read-only INTERNAL_SRAM_MMU_MULTI_HIT 26 4 read-only MEM_ACCESS_DBUG1 0x3EC 0x20 INTERNAL_SRAM_MMU_MISS 0 4 read-only ARB_IA 4 2 read-only PIDGEN_IA 6 2 read-only AHB_ACCESS_DENY 8 1 read-only AHBLITE_ACCESS_DENY 9 1 read-only AHBLITE_IA 10 1 read-only PRO_DCACHE_DBUG0 0x3F0 0x20 PRO_SLAVE_WDATA 0 1 read-write PRO_CACHE_MMU_IA 0 1 read-only PRO_CACHE_IA 1 6 read-only PRO_CACHE_STATE 7 12 read-only PRO_WR_BAK_TO_READ 19 1 read-only PRO_TX_END 20 1 read-only PRO_SLAVE_WR 21 1 read-only PRO_SLAVE_WDATA_V 22 1 read-only PRO_RX_END 23 1 read-only PRO_DCACHE_DBUG1 0x3F4 0x20 PRO_CTAG_RAM_RDATA 0 32 read-only PRO_DCACHE_DBUG2 0x3F8 0x20 PRO_CACHE_VADDR 0 27 read-only PRO_DCACHE_DBUG3 0x3FC 0x20 PRO_MMU_RDATA 0 9 read-only PRO_CPU_DISABLED_CACHE_IA 9 6 read-only PRO_CPU_DISABLED_CACHE_IA_OPPOSITE 9 1 read-write PRO_CPU_DISABLED_CACHE_IA_DRAM1 10 1 read-write PRO_CPU_DISABLED_CACHE_IA_IROM0 11 1 read-write PRO_CPU_DISABLED_CACHE_IA_IRAM1 12 1 read-write PRO_CPU_DISABLED_CACHE_IA_IRAM0 13 1 read-write PRO_CPU_DISABLED_CACHE_IA_DROM0 14 1 read-write PRO_CACHE_IRAM0_PID_ERROR 15 1 read-only PRO_DCACHE_DBUG4 0x400 0x20 PRO_DRAM1ADDR0_IA 0 20 read-only PRO_DCACHE_DBUG5 0x404 0x20 PRO_DROM0ADDR0_IA 0 20 read-only PRO_DCACHE_DBUG6 0x408 0x20 PRO_IRAM0ADDR_IA 0 20 read-only PRO_DCACHE_DBUG7 0x40C 0x20 PRO_IRAM1ADDR_IA 0 20 read-only PRO_DCACHE_DBUG8 0x410 0x20 PRO_IROM0ADDR_IA 0 20 read-only PRO_DCACHE_DBUG9 0x414 0x20 PRO_OPSDRAMADDR_IA 0 20 read-only APP_DCACHE_DBUG0 0x418 0x20 APP_SLAVE_WDATA 0 1 read-write APP_CACHE_MMU_IA 0 1 read-only APP_CACHE_IA 1 6 read-only APP_CACHE_STATE 7 12 read-only APP_WR_BAK_TO_READ 19 1 read-only APP_TX_END 20 1 read-only APP_SLAVE_WR 21 1 read-only APP_SLAVE_WDATA_V 22 1 read-only APP_RX_END 23 1 read-only APP_DCACHE_DBUG1 0x41C 0x20 APP_CTAG_RAM_RDATA 0 32 read-only APP_DCACHE_DBUG2 0x420 0x20 APP_CACHE_VADDR 0 27 read-only APP_DCACHE_DBUG3 0x424 0x20 APP_MMU_RDATA 0 9 read-only APP_CPU_DISABLED_CACHE_IA 9 6 read-only APP_CPU_DISABLED_CACHE_IA_OPPOSITE 9 1 read-write APP_CPU_DISABLED_CACHE_IA_DRAM1 10 1 read-write APP_CPU_DISABLED_CACHE_IA_IROM0 11 1 read-write APP_CPU_DISABLED_CACHE_IA_IRAM1 12 1 read-write APP_CPU_DISABLED_CACHE_IA_IRAM0 13 1 read-write APP_CPU_DISABLED_CACHE_IA_DROM0 14 1 read-write APP_CACHE_IRAM0_PID_ERROR 15 1 read-only APP_DCACHE_DBUG4 0x428 0x20 APP_DRAM1ADDR0_IA 0 20 read-only APP_DCACHE_DBUG5 0x42C 0x20 APP_DROM0ADDR0_IA 0 20 read-only APP_DCACHE_DBUG6 0x430 0x20 APP_IRAM0ADDR_IA 0 20 read-only APP_DCACHE_DBUG7 0x434 0x20 APP_IRAM1ADDR_IA 0 20 read-only APP_DCACHE_DBUG8 0x438 0x20 APP_IROM0ADDR_IA 0 20 read-only APP_DCACHE_DBUG9 0x43C 0x20 APP_OPSDRAMADDR_IA 0 20 read-only PRO_CPU_RECORD_CTRL 0x440 0x20 0x00000100 PRO_CPU_RECORD_ENABLE 0 1 read-write PRO_CPU_RECORD_DISABLE 4 1 read-write PRO_CPU_PDEBUG_ENABLE 8 1 read-write PRO_CPU_RECORD_STATUS 0x444 0x20 PRO_CPU_RECORDING 0 1 read-only PRO_CPU_RECORD_PID 0x448 0x20 RECORD_PRO_PID 0 3 read-only PRO_CPU_RECORD_PDEBUGINST 0x44C 0x20 RECORD_PRO_PDEBUGINST 0 32 read-only RECORD_PDEBUGINST_SZ 0 8 read-write RECORD_PDEBUGINST_ISRC 12 3 read-write RECORD_PDEBUGINST_LOOP_REP 20 1 read-write RECORD_PDEBUGINST_LOOP 21 1 read-write RECORD_PDEBUGINST_CINTL 24 4 read-write PRO_CPU_RECORD_PDEBUGSTATUS 0x450 0x20 RECORD_PRO_PDEBUGSTATUS 0 8 read-only RECORD_PDEBUGSTATUS_BBCAUSE 0 6 read-write RECORD_PDEBUGSTATUS_INSNTYPE 0 6 read-write PRO_CPU_RECORD_PDEBUGDATA 0x454 0x20 RECORD_PRO_PDEBUGDATA 0 32 read-only RECORD_PDEBUGDATA_DEP_OTHER 0 1 read-write RECORD_PDEBUGDATA_EXCVEC 0 5 read-write RECORD_PDEBUGDATA_INSNTYPE_SR 0 8 read-write RECORD_PDEBUGDATA_INSNTYPE_RER 0 1 read-write RECORD_PDEBUGDATA_STALL_BUFF 1 1 read-write RECORD_PDEBUGDATA_INSNTYPE_WER 1 1 read-write RECORD_PDEBUGDATA_STALL_BUFFCONFL 2 1 read-write RECORD_PDEBUGDATA_INSNTYPE_ER 2 12 read-write RECORD_PDEBUGDATA_STALL_DCM 3 1 read-write RECORD_PDEBUGDATA_STALL_LSU 4 1 read-write RECORD_PDEBUGDATA_STALL_ICM 6 1 read-write RECORD_PDEBUGDATA_STALL_IRAMBUSY 7 1 read-write RECORD_PDEBUGDATA_DEP_LSU 8 1 read-write RECORD_PDEBUGDATA_STALL_IPIF 8 1 read-write RECORD_PDEBUGDATA_INSNTYPE_RSR 8 1 read-write RECORD_PDEBUGDATA_STALL_TIE 9 1 read-write RECORD_PDEBUGDATA_INSNTYPE_WSR 9 1 read-write RECORD_PDEBUGDATA_STALL_RUN 10 1 read-write RECORD_PDEBUGDATA_INSNTYPE_XSR 10 1 read-write RECORD_PDEBUGDATA_DEP_STR 11 1 read-write RECORD_PDEBUGDATA_DEP 12 1 read-write RECORD_PDEBUGDATA_STALL_BPIFETCH 12 1 read-write RECORD_PDEBUGDATA_STALL_L32R 13 1 read-write RECORD_PDEBUGDATA_STALL_LSPROC 14 1 read-write RECORD_PDEBUGDATA_STALL_BPLOAD 15 1 read-write RECORD_PDEBUGDATA_DEP_MEMW 16 1 read-write RECORD_PDEBUGDATA_EXCCAUSE 16 6 read-write RECORD_PDEBUGDATA_STALL_BANKCONFL 16 1 read-write RECORD_PDEBUGDATA_DEP_HALT 17 1 read-write RECORD_PDEBUGDATA_STALL_ITERMUL 18 1 read-write RECORD_PDEBUGDATA_STALL_ITERDIV 19 1 read-write PRO_CPU_RECORD_PDEBUGPC 0x458 0x20 RECORD_PRO_PDEBUGPC 0 32 read-only PRO_CPU_RECORD_PDEBUGLS0STAT 0x45C 0x20 RECORD_PRO_PDEBUGLS0STAT 0 32 read-only RECORD_PDEBUGLS0STAT_TYPE 0 4 read-write RECORD_PDEBUGLS0STAT_SZ 4 4 read-write RECORD_PDEBUGLS0STAT_DTLBM 8 1 read-write RECORD_PDEBUGLS0STAT_DCM 9 1 read-write RECORD_PDEBUGLS0STAT_DCH 10 1 read-write RECORD_PDEBUGLS0STAT_UC 12 1 read-write RECORD_PDEBUGLS0STAT_WB 13 1 read-write RECORD_PDEBUGLS0STAT_COH 16 1 read-write RECORD_PDEBUGLS0STAT_STCOH 17 2 read-write RECORD_PDEBUGLS0STAT_TGT 20 4 read-write PRO_CPU_RECORD_PDEBUGLS0ADDR 0x460 0x20 RECORD_PRO_PDEBUGLS0ADDR 0 32 read-only PRO_CPU_RECORD_PDEBUGLS0DATA 0x464 0x20 RECORD_PRO_PDEBUGLS0DATA 0 32 read-only APP_CPU_RECORD_CTRL 0x468 0x20 0x00000100 APP_CPU_RECORD_ENABLE 0 1 read-write APP_CPU_RECORD_DISABLE 4 1 read-write APP_CPU_PDEBUG_ENABLE 8 1 read-write APP_CPU_RECORD_STATUS 0x46C 0x20 APP_CPU_RECORDING 0 1 read-only APP_CPU_RECORD_PID 0x470 0x20 RECORD_APP_PID 0 3 read-only APP_CPU_RECORD_PDEBUGINST 0x474 0x20 RECORD_APP_PDEBUGINST 0 32 read-only APP_CPU_RECORD_PDEBUGSTATUS 0x478 0x20 RECORD_APP_PDEBUGSTATUS 0 8 read-only APP_CPU_RECORD_PDEBUGDATA 0x47C 0x20 RECORD_APP_PDEBUGDATA 0 32 read-only APP_CPU_RECORD_PDEBUGPC 0x480 0x20 RECORD_APP_PDEBUGPC 0 32 read-only APP_CPU_RECORD_PDEBUGLS0STAT 0x484 0x20 RECORD_APP_PDEBUGLS0STAT 0 32 read-only APP_CPU_RECORD_PDEBUGLS0ADDR 0x488 0x20 RECORD_APP_PDEBUGLS0ADDR 0 32 read-only APP_CPU_RECORD_PDEBUGLS0DATA 0x48C 0x20 RECORD_APP_PDEBUGLS0DATA 0 32 read-only RSA_PD_CTRL 0x490 0x20 RSA_PD 0 1 read-write ROM_MPU_TABLE0 0x494 0x20 0x00000001 ROM_MPU_TABLE0 0 2 read-write ROM_MPU_TABLE1 0x498 0x20 0x00000001 ROM_MPU_TABLE1 0 2 read-write ROM_MPU_TABLE2 0x49C 0x20 0x00000001 ROM_MPU_TABLE2 0 2 read-write ROM_MPU_TABLE3 0x4A0 0x20 0x00000001 ROM_MPU_TABLE3 0 2 read-write SHROM_MPU_TABLE0 0x4A4 0x20 0x00000001 SHROM_MPU_TABLE0 0 2 read-write SHROM_MPU_TABLE1 0x4A8 0x20 0x00000001 SHROM_MPU_TABLE1 0 2 read-write SHROM_MPU_TABLE2 0x4AC 0x20 0x00000001 SHROM_MPU_TABLE2 0 2 read-write SHROM_MPU_TABLE3 0x4B0 0x20 0x00000001 SHROM_MPU_TABLE3 0 2 read-write SHROM_MPU_TABLE4 0x4B4 0x20 0x00000001 SHROM_MPU_TABLE4 0 2 read-write SHROM_MPU_TABLE5 0x4B8 0x20 0x00000001 SHROM_MPU_TABLE5 0 2 read-write SHROM_MPU_TABLE6 0x4BC 0x20 0x00000001 SHROM_MPU_TABLE6 0 2 read-write SHROM_MPU_TABLE7 0x4C0 0x20 0x00000001 SHROM_MPU_TABLE7 0 2 read-write SHROM_MPU_TABLE8 0x4C4 0x20 0x00000001 SHROM_MPU_TABLE8 0 2 read-write SHROM_MPU_TABLE9 0x4C8 0x20 0x00000001 SHROM_MPU_TABLE9 0 2 read-write SHROM_MPU_TABLE10 0x4CC 0x20 0x00000001 SHROM_MPU_TABLE10 0 2 read-write SHROM_MPU_TABLE11 0x4D0 0x20 0x00000001 SHROM_MPU_TABLE11 0 2 read-write SHROM_MPU_TABLE12 0x4D4 0x20 0x00000001 SHROM_MPU_TABLE12 0 2 read-write SHROM_MPU_TABLE13 0x4D8 0x20 0x00000001 SHROM_MPU_TABLE13 0 2 read-write SHROM_MPU_TABLE14 0x4DC 0x20 0x00000001 SHROM_MPU_TABLE14 0 2 read-write SHROM_MPU_TABLE15 0x4E0 0x20 0x00000001 SHROM_MPU_TABLE15 0 2 read-write SHROM_MPU_TABLE16 0x4E4 0x20 0x00000001 SHROM_MPU_TABLE16 0 2 read-write SHROM_MPU_TABLE17 0x4E8 0x20 0x00000001 SHROM_MPU_TABLE17 0 2 read-write SHROM_MPU_TABLE18 0x4EC 0x20 0x00000001 SHROM_MPU_TABLE18 0 2 read-write SHROM_MPU_TABLE19 0x4F0 0x20 0x00000001 SHROM_MPU_TABLE19 0 2 read-write SHROM_MPU_TABLE20 0x4F4 0x20 0x00000001 SHROM_MPU_TABLE20 0 2 read-write SHROM_MPU_TABLE21 0x4F8 0x20 0x00000001 SHROM_MPU_TABLE21 0 2 read-write SHROM_MPU_TABLE22 0x4FC 0x20 0x00000001 SHROM_MPU_TABLE22 0 2 read-write SHROM_MPU_TABLE23 0x500 0x20 0x00000001 SHROM_MPU_TABLE23 0 2 read-write IMMU_TABLE0 0x504 0x20 IMMU_TABLE0 0 7 read-write IMMU_TABLE1 0x508 0x20 0x00000001 IMMU_TABLE1 0 7 read-write IMMU_TABLE2 0x50C 0x20 0x00000002 IMMU_TABLE2 0 7 read-write IMMU_TABLE3 0x510 0x20 0x00000003 IMMU_TABLE3 0 7 read-write IMMU_TABLE4 0x514 0x20 0x00000004 IMMU_TABLE4 0 7 read-write IMMU_TABLE5 0x518 0x20 0x00000005 IMMU_TABLE5 0 7 read-write IMMU_TABLE6 0x51C 0x20 0x00000006 IMMU_TABLE6 0 7 read-write IMMU_TABLE7 0x520 0x20 0x00000007 IMMU_TABLE7 0 7 read-write IMMU_TABLE8 0x524 0x20 0x00000008 IMMU_TABLE8 0 7 read-write IMMU_TABLE9 0x528 0x20 0x00000009 IMMU_TABLE9 0 7 read-write IMMU_TABLE10 0x52C 0x20 0x0000000A IMMU_TABLE10 0 7 read-write IMMU_TABLE11 0x530 0x20 0x0000000B IMMU_TABLE11 0 7 read-write IMMU_TABLE12 0x534 0x20 0x0000000C IMMU_TABLE12 0 7 read-write IMMU_TABLE13 0x538 0x20 0x0000000D IMMU_TABLE13 0 7 read-write IMMU_TABLE14 0x53C 0x20 0x0000000E IMMU_TABLE14 0 7 read-write IMMU_TABLE15 0x540 0x20 0x0000000F IMMU_TABLE15 0 7 read-write DMMU_TABLE0 0x544 0x20 DMMU_TABLE0 0 7 read-write DMMU_TABLE1 0x548 0x20 0x00000001 DMMU_TABLE1 0 7 read-write DMMU_TABLE2 0x54C 0x20 0x00000002 DMMU_TABLE2 0 7 read-write DMMU_TABLE3 0x550 0x20 0x00000003 DMMU_TABLE3 0 7 read-write DMMU_TABLE4 0x554 0x20 0x00000004 DMMU_TABLE4 0 7 read-write DMMU_TABLE5 0x558 0x20 0x00000005 DMMU_TABLE5 0 7 read-write DMMU_TABLE6 0x55C 0x20 0x00000006 DMMU_TABLE6 0 7 read-write DMMU_TABLE7 0x560 0x20 0x00000007 DMMU_TABLE7 0 7 read-write DMMU_TABLE8 0x564 0x20 0x00000008 DMMU_TABLE8 0 7 read-write DMMU_TABLE9 0x568 0x20 0x00000009 DMMU_TABLE9 0 7 read-write DMMU_TABLE10 0x56C 0x20 0x0000000A DMMU_TABLE10 0 7 read-write DMMU_TABLE11 0x570 0x20 0x0000000B DMMU_TABLE11 0 7 read-write DMMU_TABLE12 0x574 0x20 0x0000000C DMMU_TABLE12 0 7 read-write DMMU_TABLE13 0x578 0x20 0x0000000D DMMU_TABLE13 0 7 read-write DMMU_TABLE14 0x57C 0x20 0x0000000E DMMU_TABLE14 0 7 read-write DMMU_TABLE15 0x580 0x20 0x0000000F DMMU_TABLE15 0 7 read-write PRO_INTRUSION_CTRL 0x584 0x20 0x00000001 PRO_INTRUSION_RECORD_RESET_N 0 1 read-write PRO_INTRUSION_STATUS 0x588 0x20 PRO_INTRUSION_RECORD 0 4 read-only APP_INTRUSION_CTRL 0x58C 0x20 0x00000001 APP_INTRUSION_RECORD_RESET_N 0 1 read-write APP_INTRUSION_STATUS 0x590 0x20 APP_INTRUSION_RECORD 0 4 read-only FRONT_END_MEM_PD 0x594 0x20 0x00000005 AGC_MEM_FORCE_PU 0 1 read-write AGC_MEM_FORCE_PD 1 1 read-write PBUS_MEM_FORCE_PU 2 1 read-write PBUS_MEM_FORCE_PD 3 1 read-write MMU_IA_INT_EN 0x598 0x20 MMU_IA_INT_EN 0 24 read-write MPU_IA_INT_EN 0x59C 0x20 MPU_IA_INT_EN 0 17 read-write CACHE_IA_INT_EN 0x5A0 0x20 CACHE_IA_INT_EN Interrupt enable bits for various invalid cache access reasons 0 28 read-write CACHE_IA_INT_APP_DROM0 APP CPU invalid access to DROM0 when cache is disabled 0 1 read-write CACHE_IA_INT_APP_IRAM0 APP CPU invalid access to IRAM0 when cache is disabled 1 1 read-write CACHE_IA_INT_APP_IRAM1 APP CPU invalid access to IRAM1 when cache is disabled 2 1 read-write CACHE_IA_INT_APP_IROM0 APP CPU invalid access to IROM0 when cache is disabled 3 1 read-write CACHE_IA_INT_APP_DRAM1 APP CPU invalid access to DRAM1 when cache is disabled 4 1 read-write CACHE_IA_INT_APP_OPPOSITE APP CPU invalid access to APP CPU cache when cache disabled 5 1 read-write CACHE_IA_INT_PRO_DROM0 PRO CPU invalid access to DROM0 when cache is disabled 14 1 read-write CACHE_IA_INT_PRO_IRAM0 PRO CPU invalid access to IRAM0 when cache is disabled 15 1 read-write CACHE_IA_INT_PRO_IRAM1 PRO CPU invalid access to IRAM1 when cache is disabled 16 1 read-write CACHE_IA_INT_PRO_IROM0 PRO CPU invalid access to IROM0 when cache is disabled 17 1 read-write CACHE_IA_INT_PRO_DRAM1 PRO CPU invalid access to DRAM1 when cache is disabled 18 1 read-write CACHE_IA_INT_PRO_OPPOSITE PRO CPU invalid access to APP CPU cache when cache disabled 19 1 read-write SECURE_BOOT_CTRL 0x5A4 0x20 SW_BOOTLOADER_SEL 0 1 read-write SPI_DMA_CHAN_SEL 0x5A8 0x20 SPI1_DMA_CHAN_SEL 0 2 read-write SPI2_DMA_CHAN_SEL 2 2 read-write SPI3_DMA_CHAN_SEL 4 2 read-write PRO_VECBASE_CTRL 0x5AC 0x20 PRO_OUT_VECBASE_SEL 0 2 read-write PRO_VECBASE_SET 0x5B0 0x20 PRO_OUT_VECBASE 0 22 read-write APP_VECBASE_CTRL 0x5B4 0x20 APP_OUT_VECBASE_SEL 0 2 read-write APP_VECBASE_SET 0x5B8 0x20 APP_OUT_VECBASE 0 22 read-write DATE 0xFFC 0x20 0x01605190 DATE 0 28 read-write EFUSE eFuse Controller EFUSE 0x3FF5A000 0x0 0x124 registers EFUSE 44 BLK0_RDATA0 0x0 0x20 RD_EFUSE_WR_DIS read for efuse_wr_disable 0 16 read-only RD_EFUSE_RD_DIS read for efuse_rd_disable 16 4 read-only RD_FLASH_CRYPT_CNT read for flash_crypt_cnt 20 7 read-only BLK0_RDATA1 0x4 0x20 RD_WIFI_MAC_CRC_LOW read for low 32bit WIFI_MAC_Address 0 32 read-only BLK0_RDATA2 0x8 0x20 RD_WIFI_MAC_CRC_HIGH read for high 24bit WIFI_MAC_Address 0 24 read-only BLK0_RDATA3 0xC 0x20 RD_CHIP_VER_DIS_APP_CPU 0 1 read-only RD_CHIP_VER_DIS_BT 1 1 read-only RD_CHIP_VER_PKG_4BIT most significant bit of chip package 2 1 read-only RD_CHIP_VER_DIS_CACHE 3 1 read-only RD_SPI_PAD_CONFIG_HD read for SPI_pad_config_hd 4 5 read-only RD_CHIP_VER_PKG least significant bits of chip package 9 3 read-write RD_CHIP_CPU_FREQ_LOW If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise 12 1 read-write RD_CHIP_CPU_FREQ_RATED If set, the ESP32's maximum CPU frequency has been rated 13 1 read-write RD_BLK3_PART_RESERVE If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 14 1 read-write RD_CHIP_VER_REV1 bit is set to 1 for rev1 silicon 15 1 read-write BLK0_RDATA4 0x10 0x20 RD_CK8M_FREQ 0 8 read-only RD_ADC_VREF True ADC reference voltage 8 5 read-write RD_SDIO_DREFH 8 2 read-only RD_SDIO_DREFM 10 2 read-only RD_SDIO_DREFL 12 2 read-only RD_XPD_SDIO read for XPD_SDIO_REG 14 1 read-only RD_SDIO_TIEH read for SDIO_TIEH 15 1 read-only RD_SDIO_FORCE read for sdio_force 16 1 read-only BLK0_RDATA5 0x14 0x20 RD_SPI_PAD_CONFIG_CLK read for SPI_pad_config_clk 0 5 read-only RD_SPI_PAD_CONFIG_Q read for SPI_pad_config_q 5 5 read-only RD_SPI_PAD_CONFIG_D read for SPI_pad_config_d 10 5 read-only RD_SPI_PAD_CONFIG_CS0 read for SPI_pad_config_cs0 15 5 read-only RD_CHIP_VER_REV2 20 1 read-only RD_VOL_LEVEL_HP_INV This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 22 2 read-only RD_WAFER_VERSION_MINOR 24 2 read-only RD_FLASH_CRYPT_CONFIG read for flash_crypt_config 28 4 read-only BLK0_RDATA6 0x18 0x20 RD_CODING_SCHEME read for coding_scheme 0 2 read-only RD_CONSOLE_DEBUG_DISABLE read for console_debug_disable 2 1 read-only RD_DISABLE_SDIO_HOST 3 1 read-only RD_ABS_DONE_0 read for abstract_done_0 4 1 read-only RD_ABS_DONE_1 read for abstract_done_1 5 1 read-only RD_DISABLE_JTAG read for JTAG_disable 6 1 read-only RD_DISABLE_DL_ENCRYPT read for download_dis_encrypt 7 1 read-only RD_DISABLE_DL_DECRYPT read for download_dis_decrypt 8 1 read-only RD_DISABLE_DL_CACHE read for download_dis_cache 9 1 read-only RD_KEY_STATUS read for key_status 10 1 read-only BLK0_WDATA0 0x1C 0x20 WR_DIS program for efuse_wr_disable 0 16 read-write RD_DIS program for efuse_rd_disable 16 4 read-write FLASH_CRYPT_CNT program for flash_crypt_cnt 20 7 read-write BLK0_WDATA1 0x20 0x20 WIFI_MAC_CRC_LOW program for low 32bit WIFI_MAC_Address 0 32 read-write BLK0_WDATA2 0x24 0x20 WIFI_MAC_CRC_HIGH program for high 24bit WIFI_MAC_Address 0 24 read-write BLK0_WDATA3 0x28 0x20 CHIP_VER_DIS_APP_CPU 0 1 read-write CHIP_VER_DIS_BT 1 1 read-write CHIP_VER_PKG_4BIT most significant bit of chip package 2 1 read-only CHIP_VER_DIS_CACHE 3 1 read-write SPI_PAD_CONFIG_HD program for SPI_pad_config_hd 4 5 read-write CHIP_VER_PKG least significant bits of chip package 9 3 read-write CHIP_CPU_FREQ_LOW If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise 12 1 read-write CHIP_CPU_FREQ_RATED If set, the ESP32's maximum CPU frequency has been rated 13 1 read-write BLK3_PART_RESERVE If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 14 1 read-write CHIP_VER_REV1 15 1 read-write BLK0_WDATA4 0x2C 0x20 CK8M_FREQ 0 8 read-write ADC_VREF True ADC reference voltage 8 5 read-write SDIO_DREFH 8 2 read-write SDIO_DREFM 10 2 read-write SDIO_DREFL 12 2 read-write XPD_SDIO program for XPD_SDIO_REG 14 1 read-write SDIO_TIEH program for SDIO_TIEH 15 1 read-write SDIO_FORCE program for sdio_force 16 1 read-write BLK0_WDATA5 0x30 0x20 SPI_PAD_CONFIG_CLK program for SPI_pad_config_clk 0 5 read-write SPI_PAD_CONFIG_Q program for SPI_pad_config_q 5 5 read-write SPI_PAD_CONFIG_D program for SPI_pad_config_d 10 5 read-write SPI_PAD_CONFIG_CS0 program for SPI_pad_config_cs0 15 5 read-write INST_CONFIG 20 8 read-write VOL_LEVEL_HP_INV This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W) 22 2 read-write DIG_VOL_L6 24 4 read-write FLASH_CRYPT_CONFIG program for flash_crypt_config 28 4 read-write BLK0_WDATA6 0x34 0x20 CODING_SCHEME program for coding_scheme 0 2 read-write CONSOLE_DEBUG_DISABLE program for console_debug_disable 2 1 read-write DISABLE_SDIO_HOST 3 1 read-write ABS_DONE_0 program for abstract_done_0 4 1 read-write ABS_DONE_1 program for abstract_done_1 5 1 read-write DISABLE_JTAG program for JTAG_disable 6 1 read-write DISABLE_DL_ENCRYPT program for download_dis_encrypt 7 1 read-write DISABLE_DL_DECRYPT program for download_dis_decrypt 8 1 read-write DISABLE_DL_CACHE program for download_dis_cache 9 1 read-write KEY_STATUS program for key_status 10 1 read-write BLK1_RDATA0 0x38 0x20 BLK1_DOUT0 read for BLOCK1 0 32 read-only BLK1_RDATA1 0x3C 0x20 BLK1_DOUT1 read for BLOCK1 0 32 read-only BLK1_RDATA2 0x40 0x20 BLK1_DOUT2 read for BLOCK1 0 32 read-only BLK1_RDATA3 0x44 0x20 BLK1_DOUT3 read for BLOCK1 0 32 read-only BLK1_RDATA4 0x48 0x20 BLK1_DOUT4 read for BLOCK1 0 32 read-only BLK1_RDATA5 0x4C 0x20 BLK1_DOUT5 read for BLOCK1 0 32 read-only BLK1_RDATA6 0x50 0x20 BLK1_DOUT6 read for BLOCK1 0 32 read-only BLK1_RDATA7 0x54 0x20 BLK1_DOUT7 read for BLOCK1 0 32 read-only BLK2_RDATA0 0x58 0x20 BLK2_DOUT0 read for BLOCK2 0 32 read-only BLK2_RDATA1 0x5C 0x20 BLK2_DOUT1 read for BLOCK2 0 32 read-only BLK2_RDATA2 0x60 0x20 BLK2_DOUT2 read for BLOCK2 0 32 read-only BLK2_RDATA3 0x64 0x20 BLK2_DOUT3 read for BLOCK2 0 32 read-only BLK2_RDATA4 0x68 0x20 BLK2_DOUT4 read for BLOCK2 0 32 read-only BLK2_RDATA5 0x6C 0x20 BLK2_DOUT5 read for BLOCK2 0 32 read-only BLK2_RDATA6 0x70 0x20 BLK2_DOUT6 read for BLOCK2 0 32 read-only BLK2_RDATA7 0x74 0x20 BLK2_DOUT7 read for BLOCK2 0 32 read-only BLK3_RDATA0 0x78 0x20 BLK3_DOUT0 read for BLOCK3 0 32 read-only BLK3_RDATA1 0x7C 0x20 BLK3_DOUT1 read for BLOCK3 0 32 read-only BLK3_RDATA2 0x80 0x20 BLK3_DOUT2 read for BLOCK3 0 32 read-only BLK3_RDATA3 0x84 0x20 BLK3_DOUT3 read for BLOCK3 0 32 read-only RD_ADC1_TP_LOW ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 0 7 read-write RD_ADC1_TP_HIGH ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 7 9 read-write RD_ADC2_TP_LOW ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 16 7 read-write RD_ADC2_TP_HIGH ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 23 9 read-write BLK3_RDATA4 0x88 0x20 BLK3_DOUT4 read for BLOCK3 0 32 read-only RD_CAL_RESERVED Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE 0 16 read-write BLK3_RDATA5 0x8C 0x20 BLK3_DOUT5 read for BLOCK3 0 32 read-only BLK3_RDATA6 0x90 0x20 BLK3_DOUT6 read for BLOCK3 0 32 read-only BLK3_RDATA7 0x94 0x20 BLK3_DOUT7 read for BLOCK3 0 32 read-only BLK1_WDATA0 0x98 0x20 BLK1_DIN0 program for BLOCK1 0 32 read-write BLK1_WDATA1 0x9C 0x20 BLK1_DIN1 program for BLOCK1 0 32 read-write BLK1_WDATA2 0xA0 0x20 BLK1_DIN2 program for BLOCK1 0 32 read-write BLK1_WDATA3 0xA4 0x20 BLK1_DIN3 program for BLOCK1 0 32 read-write BLK1_WDATA4 0xA8 0x20 BLK1_DIN4 program for BLOCK1 0 32 read-write BLK1_WDATA5 0xAC 0x20 BLK1_DIN5 program for BLOCK1 0 32 read-write BLK1_WDATA6 0xB0 0x20 BLK1_DIN6 program for BLOCK1 0 32 read-write BLK1_WDATA7 0xB4 0x20 BLK1_DIN7 program for BLOCK1 0 32 read-write BLK2_WDATA0 0xB8 0x20 BLK2_DIN0 program for BLOCK2 0 32 read-write BLK2_WDATA1 0xBC 0x20 BLK2_DIN1 program for BLOCK2 0 32 read-write BLK2_WDATA2 0xC0 0x20 BLK2_DIN2 program for BLOCK2 0 32 read-write BLK2_WDATA3 0xC4 0x20 BLK2_DIN3 program for BLOCK2 0 32 read-write BLK2_WDATA4 0xC8 0x20 BLK2_DIN4 program for BLOCK2 0 32 read-write BLK2_WDATA5 0xCC 0x20 BLK2_DIN5 program for BLOCK2 0 32 read-write BLK2_WDATA6 0xD0 0x20 BLK2_DIN6 program for BLOCK2 0 32 read-write BLK2_WDATA7 0xD4 0x20 BLK2_DIN7 program for BLOCK2 0 32 read-write BLK3_WDATA0 0xD8 0x20 BLK3_DIN0 program for BLOCK3 0 32 read-write BLK3_WDATA1 0xDC 0x20 BLK3_DIN1 program for BLOCK3 0 32 read-write BLK3_WDATA2 0xE0 0x20 BLK3_DIN2 program for BLOCK3 0 32 read-write BLK3_WDATA3 0xE4 0x20 BLK3_DIN3 program for BLOCK3 0 32 read-write ADC1_TP_LOW ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 0 7 read-write ADC1_TP_HIGH ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 7 9 read-write ADC2_TP_LOW ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 16 7 read-write ADC2_TP_HIGH ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 23 9 read-write BLK3_WDATA4 0xE8 0x20 BLK3_DIN4 program for BLOCK3 0 32 read-write CAL_RESERVED Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE 0 16 read-write BLK3_WDATA5 0xEC 0x20 BLK3_DIN5 program for BLOCK3 0 32 read-write BLK3_WDATA6 0xF0 0x20 BLK3_DIN6 program for BLOCK3 0 32 read-write BLK3_WDATA7 0xF4 0x20 BLK3_DIN7 program for BLOCK3 0 32 read-write CLK 0xF8 0x20 0x00004052 SEL0 efuse timing configure 0 8 read-write SEL1 efuse timing configure 8 8 read-write EN 16 1 read-write CONF 0xFC 0x20 0x00010000 OP_CODE efuse operation code 0 16 read-write FORCE_NO_WR_RD_DIS 16 1 read-write STATUS 0x100 0x20 DEBUG 0 32 read-only CMD 0x104 0x20 READ_CMD command for read 0 1 read-write PGM_CMD command for program 1 1 read-write INT_RAW 0x108 0x20 READ_DONE_INT_RAW read done interrupt raw status 0 1 read-only PGM_DONE_INT_RAW program done interrupt raw status 1 1 read-only INT_ST 0x10C 0x20 READ_DONE_INT_ST read done interrupt status 0 1 read-only PGM_DONE_INT_ST program done interrupt status 1 1 read-only INT_ENA 0x110 0x20 READ_DONE_INT_ENA read done interrupt enable 0 1 read-write PGM_DONE_INT_ENA program done interrupt enable 1 1 read-write INT_CLR 0x114 0x20 READ_DONE_INT_CLR read done interrupt clear 0 1 write-only PGM_DONE_INT_CLR program done interrupt clear 1 1 write-only DAC_CONF 0x118 0x20 0x00000028 DAC_CLK_DIV efuse timing configure 0 8 read-write DAC_CLK_PAD_SEL 8 1 read-write DEC_STATUS 0x11C 0x20 DEC_WARNINGS the decode result of 3/4 coding scheme has warning 0 12 read-only DATE 0x1FC 0x20 0x16042600 DATE 0 32 read-write FLASH_ENCRYPTION Flash Encryption Peripheral FLASH_ENCRYPTION 0x3FF46000 0x0 0x2C registers 8 0x4 BUFFER_%s 0x0 0x20 BUFFER Data buffers for encryption. 0 8 write-only START 0x20 0x20 FLASH_START Set this bit to start encryption operation on data buffer. 0 8 write-only ADDRESS 0x24 0x20 ADDRESS The physical address on the off-chip flash must be 8-word boundary aligned. 0 8 write-only DONE 0x28 0x20 FLASH_DONE Set this bit when encryption operation is complete. 0 1 read-only FRC_TIMER Peripheral FRC_TIMER FRC 0x3FF47000 0x0 0x14 registers TIMER_LOAD 0x0 0x20 VALUE 0 8 read-write TIMER_COUNT 0x4 0x20 TIMER_COUNT 0 8 read-write TIMER_CTRL 0x8 0x20 TIMER_PRESCALER 1 8 read-write TIMER_INT 0xC 0x20 CLR 0 1 read-write TIMER_ALARM 0x10 0x20 TIMER_ALARM 0 8 read-write GPIO General Purpose Input/Output GPIO 0x3FF44000 0x0 0x5CC registers GPIO 22 GPIO_NMI 23 BT_SELECT 0x0 0x20 BT_SEL NA 0 32 read-write OUT 0x4 0x20 DATA GPIO0~31 output value 0 32 read-write OUT_W1TS 0x8 0x20 OUT_DATA_W1TS GPIO0~31 output value write 1 to set 0 32 read-write OUT_W1TC 0xC 0x20 OUT_DATA_W1TC GPIO0~31 output value write 1 to clear 0 32 read-write OUT1 0x10 0x20 DATA GPIO32~39 output value 0 8 read-write OUT1_W1TS 0x14 0x20 OUT1_DATA_W1TS GPIO32~39 output value write 1 to set 0 8 read-write OUT1_W1TC 0x18 0x20 OUT1_DATA_W1TC GPIO32~39 output value write 1 to clear 0 8 read-write SDIO_SELECT 0x1C 0x20 SDIO_SEL SDIO PADS on/off control from outside 0 8 read-write ENABLE 0x20 0x20 DATA GPIO0~31 output enable 0 32 read-write ENABLE_W1TS 0x24 0x20 ENABLE_DATA_W1TS GPIO0~31 output enable write 1 to set 0 32 read-write ENABLE_W1TC 0x28 0x20 ENABLE_DATA_W1TC GPIO0~31 output enable write 1 to clear 0 32 read-write ENABLE1 0x2C 0x20 DATA GPIO32~39 output enable 0 8 read-write ENABLE1_W1TS 0x30 0x20 ENABLE1_DATA_W1TS GPIO32~39 output enable write 1 to set 0 8 read-write ENABLE1_W1TC 0x34 0x20 ENABLE1_DATA_W1TC GPIO32~39 output enable write 1 to clear 0 8 read-write STRAP 0x38 0x20 STRAPPING {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} 0 16 read-only IN 0x3C 0x20 DATA_NEXT GPIO0~31 input value 0 32 read-write IN1 0x40 0x20 DATA_NEXT GPIO32~39 input value 0 8 read-write STATUS 0x44 0x20 INT GPIO0~31 interrupt status 0 32 read-write STATUS_W1TS 0x48 0x20 STATUS_INT_W1TS GPIO0~31 interrupt status write 1 to set 0 32 read-write STATUS_W1TC 0x4C 0x20 STATUS_INT_W1TC GPIO0~31 interrupt status write 1 to clear 0 32 read-write STATUS1 0x50 0x20 INT GPIO32~39 interrupt status 0 8 read-write STATUS1_W1TS 0x54 0x20 STATUS1_INT_W1TS GPIO32~39 interrupt status write 1 to set 0 8 read-write STATUS1_W1TC 0x58 0x20 STATUS1_INT_W1TC GPIO32~39 interrupt status write 1 to clear 0 8 read-write ACPU_INT 0x60 0x20 APPCPU_INT GPIO0~31 APP CPU interrupt status 0 32 read-only ACPU_NMI_INT 0x64 0x20 APPCPU_NMI_INT GPIO0~31 APP CPU non-maskable interrupt status 0 32 read-only PCPU_INT 0x68 0x20 PROCPU_INT GPIO0~31 PRO CPU interrupt status 0 32 read-only PCPU_NMI_INT 0x6C 0x20 PROCPU_NMI_INT GPIO0~31 PRO CPU non-maskable interrupt status 0 32 read-only CPUSDIO_INT 0x70 0x20 SDIO_INT SDIO's extent GPIO0~31 interrupt 0 32 read-only ACPU_INT1 0x74 0x20 APPCPU_INT_H GPIO32~39 APP CPU interrupt status 0 8 read-only ACPU_NMI_INT1 0x78 0x20 APPCPU_NMI_INT_H GPIO32~39 APP CPU non-maskable interrupt status 0 8 read-only PCPU_INT1 0x7C 0x20 PROCPU_INT_H GPIO32~39 PRO CPU interrupt status 0 8 read-only PCPU_NMI_INT1 0x80 0x20 PROCPU_NMI_INT_H GPIO32~39 PRO CPU non-maskable interrupt status 0 8 read-only CPUSDIO_INT1 0x84 0x20 SDIO_INT_H SDIO's extent GPIO32~39 interrupt 0 8 read-only PIN_PAD_DRIVER 2 1 read-write PIN_INT_TYPE 7 3 read-write PIN_WAKEUP_ENABLE 10 1 read-write PIN_CONFIG 11 2 read-write PIN_INT_ENA 13 5 read-write 40 0x4 0-39 PIN%s 0x88 0x20 PAD_DRIVER if set to 0: normal output if set to 1: open drain 2 1 read-write INT_TYPE if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger 7 3 read-write WAKEUP_ENABLE GPIO wake up enable only available in light sleep 10 1 read-write CONFIG NA 11 2 read-write INT_ENA bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable 13 5 read-write cali_conf 0x128 0x20 CALI_RTC_MAX 0 10 read-write CALI_START 31 1 read-write cali_data 0x12C 0x20 CALI_VALUE_SYNC2 0 20 read-only CALI_RDY_REAL 30 1 read-only CALI_RDY_SYNC2 31 1 read-only 256 0x4 0-255 FUNC%s_IN_SEL_CFG 0x130 0x20 IN_SEL select one of the 256 inputs 0 6 read-write IN_INV_SEL revert the value of the input if you want to revert please set the value to 1 6 1 read-write SEL if the slow signal bypass the io matrix or not if you want setting the value to 1 7 1 read-write 40 0x4 0-39 FUNC%s_OUT_SEL_CFG 0x530 0x20 OUT_SEL select one of the 256 output to 40 GPIO 0 9 read-write INV_SEL invert the output value if you want to revert the output value setting the value to 1 9 1 read-write OEN_SEL weather using the logical oen signal or not using the value setting by the register 10 1 read-write OEN_INV_SEL invert the output enable value if you want to revert the output enable value setting the value to 1 11 1 read-write GPIO_SD Sigma-Delta Modulation GPIO_SIGMADELTA 0x3FF44F00 0x0 0x2C registers SIGMADELTA0 0x0 0x20 0x0000FF00 SD0_IN 0 8 read-write SD0_PRESCALE 8 8 read-write SIGMADELTA1 0x4 0x20 0x0000FF00 SD1_IN 0 8 read-write SD1_PRESCALE 8 8 read-write SIGMADELTA2 0x8 0x20 0x0000FF00 SD2_IN 0 8 read-write SD2_PRESCALE 8 8 read-write SIGMADELTA3 0xC 0x20 0x0000FF00 SD3_IN 0 8 read-write SD3_PRESCALE 8 8 read-write SIGMADELTA4 0x10 0x20 0x0000FF00 SD4_IN 0 8 read-write SD4_PRESCALE 8 8 read-write SIGMADELTA5 0x14 0x20 0x0000FF00 SD5_IN 0 8 read-write SD5_PRESCALE 8 8 read-write SIGMADELTA6 0x18 0x20 0x0000FF00 SD6_IN 0 8 read-write SD6_PRESCALE 8 8 read-write SIGMADELTA7 0x1C 0x20 0x0000FF00 SD7_IN 0 8 read-write SD7_PRESCALE 8 8 read-write CG 0x20 0x20 SD_CLK_EN 31 1 read-write MISC 0x24 0x20 SPI_SWAP 31 1 read-write VERSION 0x28 0x20 0x01506190 SD_DATE 0 28 read-write HINF Peripheral HINF HINF 0x3FF4B000 0x0 0x34 registers CFG_DATA0 0x0 0x20 0x22226666 USER_ID_FN1 0 16 read-write DEVICE_ID_FN1 16 16 read-write CFG_DATA1 0x4 0x20 0x01110011 SDIO_ENABLE 0 1 read-write SDIO_IOREADY1 1 1 read-write HIGHSPEED_ENABLE 2 1 read-write HIGHSPEED_MODE 3 1 read-only SDIO_CD_ENABLE 4 1 read-write SDIO_IOREADY2 5 1 read-write SDIO_INT_MASK 6 1 read-write IOENABLE2 7 1 read-only CD_DISABLE 8 1 read-only FUNC1_EPS 9 1 read-only EMP 10 1 read-only IOENABLE1 11 1 read-only SDIO20_CONF0 12 4 read-write SDIO_VER 16 12 read-write FUNC2_EPS 28 1 read-only SDIO20_CONF1 29 3 read-write CFG_DATA7 0x1C 0x20 0x00020000 PIN_STATE 0 8 read-write CHIP_STATE 8 8 read-write SDIO_RST 16 1 read-write SDIO_IOREADY0 17 1 read-write CIS_CONF0 0x20 0x20 0xFFFFFFFF CIS_CONF_W0 0 32 read-write CIS_CONF1 0x24 0x20 0xFFFFFFFF CIS_CONF_W1 0 32 read-write CIS_CONF2 0x28 0x20 0xFFFFFFFF CIS_CONF_W2 0 32 read-write CIS_CONF3 0x2C 0x20 0xFFFFFFFF CIS_CONF_W3 0 32 read-write CIS_CONF4 0x30 0x20 0xFFFFFFFF CIS_CONF_W4 0 32 read-write CIS_CONF5 0x34 0x20 0xFFFFFFFF CIS_CONF_W5 0 32 read-write CIS_CONF6 0x38 0x20 0xFFFFFFFF CIS_CONF_W6 0 32 read-write CIS_CONF7 0x3C 0x20 0xFFFFFFFF CIS_CONF_W7 0 32 read-write CFG_DATA16 0x40 0x20 0x33336666 USER_ID_FN2 0 16 read-write DEVICE_ID_FN2 16 16 read-write DATE 0xFC 0x20 0x15030200 SDIO_DATE 0 32 read-write I2C0 I2C (Inter-Integrated Circuit) Controller I2C 0x3FF53000 0x0 0x9C registers I2C_EXT0 49 SCL_LOW_PERIOD 0x0 0x20 SCL_LOW_PERIOD This register is used to configure the low level width of SCL clock. 0 14 read-write CTR 0x4 0x20 0x00000003 SDA_FORCE_OUT 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal) 0 1 read-write SCL_FORCE_OUT 1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal) 1 1 read-write SAMPLE_SCL_LEVEL Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level. 2 1 read-write MS_MODE Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave. 4 1 read-write TRANS_START Set this bit to start sending data in txfifo. 5 1 read-write TX_LSB_FIRST This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit 6 1 read-write RX_LSB_FIRST This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit 7 1 read-write CLK_EN This is the clock gating control bit for reading or writing registers. 8 1 read-write SR 0x8 0x20 ACK_REC This register stores the value of ACK bit. 0 1 read-only SLAVE_RW when in slave mode 1: master read slave 0: master write slave. 1 1 read-only TIME_OUT when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level. 2 1 read-only ARB_LOST when I2C lost control of SDA line this register changes to high level. 3 1 read-only BUS_BUSY 1:I2C bus is busy transferring data. 0:I2C bus is in idle state. 4 1 read-only SLAVE_ADDRESSED when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level. 5 1 read-only BYTE_TRANS This register changes to high level when one byte is transferred. 6 1 read-only RXFIFO_CNT This register represent the amount of data need to send. 8 6 read-only TXFIFO_CNT This register stores the amount of received data in ram. 18 6 read-only SCL_MAIN_STATE_LAST This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK 24 3 read-only SCL_STATE_LAST This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP 28 3 read-only TO 0xC 0x20 TIME_OUT This register is used to configure the max clock number of receiving a data. 0 20 read-write SLAVE_ADDR 0x10 0x20 SLAVE_ADDR when configured as i2c slave this register is used to configure slave's address. 0 15 read-write ADDR_10BIT_EN This register is used to enable slave 10bit address mode. 31 1 read-write RXFIFO_ST 0x14 0x20 RXFIFO_START_ADDR This is the offset address of the last receiving data as described in nonfifo_rx_thres_register. 0 5 read-only RXFIFO_END_ADDR This is the offset address of the first receiving data as described in nonfifo_rx_thres_register. 5 5 read-only TXFIFO_START_ADDR This is the offset address of the first sending data as described in nonfifo_tx_thres register. 10 5 read-only TXFIFO_END_ADDR This is the offset address of the last sending data as described in nonfifo_tx_thres register. 15 5 read-only FIFO_CONF 0x18 0x20 0x0155408B RXFIFO_FULL_THRHD 0 5 read-write TXFIFO_EMPTY_THRHD Config txfifo empty threhd value when using apb fifo access 5 5 read-write NONFIFO_EN Set this bit to enble apb nonfifo access. 10 1 read-write FIFO_ADDR_CFG_EN When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. 11 1 read-write RX_FIFO_RST Set this bit to reset rx fifo when using apb fifo access. 12 1 read-write TX_FIFO_RST Set this bit to reset tx fifo when using apb fifo access. 13 1 read-write NONFIFO_RX_THRES when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data. 14 6 read-write NONFIFO_TX_THRES when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. 20 6 read-write DATA 0x1C 0x20 FIFO_RDATA The register represent the byte data read from rxfifo when use apb fifo access 0 8 read-only INT_RAW 0x20 0x20 RXFIFO_FULL_INT_RAW The raw interrupt status bit for rxfifo full when use apb fifo access. 0 1 read-only TXFIFO_EMPTY_INT_RAW The raw interrupt status bit for txfifo empty when use apb fifo access. 1 1 read-only RXFIFO_OVF_INT_RAW The raw interrupt status bit for receiving data overflow when use apb fifo access. 2 1 read-only END_DETECT_INT_RAW The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt. 3 1 read-only SLAVE_TRAN_COMP_INT_RAW The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt. 4 1 read-only ARBITRATION_LOST_INT_RAW The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt. 5 1 read-only MASTER_TRAN_COMP_INT_RAW The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt. 6 1 read-only TRANS_COMPLETE_INT_RAW The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt. 7 1 read-only TIME_OUT_INT_RAW The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt. 8 1 read-only TRANS_START_INT_RAW The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt. 9 1 read-only ACK_ERR_INT_RAW The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt.. 10 1 read-only RX_REC_FULL_INT_RAW The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt. 11 1 read-only TX_SEND_EMPTY_INT_RAW The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt.. 12 1 read-only INT_CLR 0x24 0x20 RXFIFO_FULL_INT_CLR Set this bit to clear the rxfifo_full_int interrupt. 0 1 write-only TXFIFO_EMPTY_INT_CLR Set this bit to clear the txfifo_empty_int interrupt. 1 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear the rxfifo_ovf_int interrupt. 2 1 write-only END_DETECT_INT_CLR Set this bit to clear the end_detect_int interrupt. 3 1 write-only SLAVE_TRAN_COMP_INT_CLR Set this bit to clear the slave_tran_comp_int interrupt. 4 1 write-only ARBITRATION_LOST_INT_CLR Set this bit to clear the arbitration_lost_int interrupt. 5 1 write-only MASTER_TRAN_COMP_INT_CLR Set this bit to clear the master_tran_comp interrupt. 6 1 write-only TRANS_COMPLETE_INT_CLR Set this bit to clear the trans_complete_int interrupt. 7 1 write-only TIME_OUT_INT_CLR Set this bit to clear the time_out_int interrupt. 8 1 write-only TRANS_START_INT_CLR Set this bit to clear the trans_start_int interrupt. 9 1 write-only ACK_ERR_INT_CLR Set this bit to clear the ack_err_int interrupt. 10 1 write-only RX_REC_FULL_INT_CLR Set this bit to clear the rx_rec_full_int interrupt. 11 1 write-only TX_SEND_EMPTY_INT_CLR Set this bit to clear the tx_send_empty_int interrupt. 12 1 write-only INT_ENA 0x28 0x20 RXFIFO_FULL_INT_ENA The enable bit for rxfifo_full_int interrupt. 0 1 read-write TXFIFO_EMPTY_INT_ENA The enable bit for txfifo_empty_int interrupt. 1 1 read-write RXFIFO_OVF_INT_ENA The enable bit for rxfifo_ovf_int interrupt. 2 1 read-write END_DETECT_INT_ENA The enable bit for end_detect_int interrupt. 3 1 read-write SLAVE_TRAN_COMP_INT_ENA The enable bit for slave_tran_comp_int interrupt. 4 1 read-write ARBITRATION_LOST_INT_ENA The enable bit for arbitration_lost_int interrupt. 5 1 read-write MASTER_TRAN_COMP_INT_ENA The enable bit for master_tran_comp_int interrupt. 6 1 read-write TRANS_COMPLETE_INT_ENA The enable bit for trans_complete_int interrupt. 7 1 read-write TIME_OUT_INT_ENA The enable bit for time_out_int interrupt. 8 1 read-write TRANS_START_INT_ENA The enable bit for trans_start_int interrupt. 9 1 read-write ACK_ERR_INT_ENA The enable bit for ack_err_int interrupt. 10 1 read-write RX_REC_FULL_INT_ENA The enable bit for rx_rec_full_int interrupt. 11 1 read-write TX_SEND_EMPTY_INT_ENA The enable bit for tx_send_empty_int interrupt. 12 1 read-write INT_STATUS 0x2C 0x20 RXFIFO_FULL_INT_ST The masked interrupt status for rxfifo_full_int interrupt. 0 1 read-only TXFIFO_EMPTY_INT_ST The masked interrupt status for txfifo_empty_int interrupt. 1 1 read-only RXFIFO_OVF_INT_ST The masked interrupt status for rxfifo_ovf_int interrupt. 2 1 read-only END_DETECT_INT_ST The masked interrupt status for end_detect_int interrupt. 3 1 read-only SLAVE_TRAN_COMP_INT_ST The masked interrupt status for slave_tran_comp_int interrupt. 4 1 read-only ARBITRATION_LOST_INT_ST The masked interrupt status for arbitration_lost_int interrupt. 5 1 read-only MASTER_TRAN_COMP_INT_ST The masked interrupt status for master_tran_comp_int interrupt. 6 1 read-only TRANS_COMPLETE_INT_ST The masked interrupt status for trans_complete_int interrupt. 7 1 read-only TIME_OUT_INT_ST The masked interrupt status for time_out_int interrupt. 8 1 read-only TRANS_START_INT_ST The masked interrupt status for trans_start_int interrupt. 9 1 read-only ACK_ERR_INT_ST The masked interrupt status for ack_err_int interrupt. 10 1 read-only RX_REC_FULL_INT_ST The masked interrupt status for rx_rec_full_int interrupt. 11 1 read-only TX_SEND_EMPTY_INT_ST The masked interrupt status for tx_send_empty_int interrupt. 12 1 read-only SDA_HOLD 0x30 0x20 TIME This register is used to configure the clock num I2C used to hold the data after the negedge of SCL. 0 10 read-write SDA_SAMPLE 0x34 0x20 TIME This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL 0 10 read-write SCL_HIGH_PERIOD 0x38 0x20 SCL_HIGH_PERIOD This register is used to configure the clock num during SCL is low level. 0 14 read-write SCL_START_HOLD 0x40 0x20 0x00000008 TIME This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark. 0 10 read-write SCL_RSTART_SETUP 0x44 0x20 0x00000008 TIME This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark. 0 10 read-write SCL_STOP_HOLD 0x48 0x20 TIME This register is used to configure the clock num after the STOP bit's posedge. 0 14 read-write SCL_STOP_SETUP 0x4C 0x20 TIME This register is used to configure the clock num between the posedge of SCL and the posedge of SDA. 0 10 read-write SCL_FILTER_CFG 0x50 0x20 0x00000008 SCL_FILTER_THRES When input SCL's pulse width is smaller than this register value I2C ignores this pulse. 0 3 read-write SCL_FILTER_EN This is the filter enable bit for SCL. 3 1 read-write SDA_FILTER_CFG 0x54 0x20 0x00000008 SDA_FILTER_THRES When input SCL's pulse width is smaller than this register value I2C ignores this pulse. 0 3 read-write SDA_FILTER_EN This is the filter enable bit for SDA. 3 1 read-write 16 0x4 0-15 COMD%s 0x58 0x20 COMMAND This is the content of command0. It consists of three part. op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit. 0 14 read-write COMMAND_DONE When command0 is done in I2C Master mode this bit changes to high level. 31 1 read-write DATE 0xF8 0x20 0x16042000 DATE 0 32 read-write FIFO_START_ADDR 0x100 0x20 I2C1 I2C (Inter-Integrated Circuit) Controller 0x3FF67000 I2C_EXT1 50 I2S0 I2S (Inter-IC Sound) Controller I2S 0x3FF4F000 0x0 0xB4 registers I2S0 32 CONF 0x8 0x20 0x00030300 TX_RESET 0 1 read-write RX_RESET 1 1 read-write TX_FIFO_RESET 2 1 read-write RX_FIFO_RESET 3 1 read-write TX_START 4 1 read-write RX_START 5 1 read-write TX_SLAVE_MOD 6 1 read-write RX_SLAVE_MOD 7 1 read-write TX_RIGHT_FIRST 8 1 read-write RX_RIGHT_FIRST 9 1 read-write TX_MSB_SHIFT 10 1 read-write RX_MSB_SHIFT 11 1 read-write TX_SHORT_SYNC 12 1 read-write RX_SHORT_SYNC 13 1 read-write TX_MONO 14 1 read-write RX_MONO 15 1 read-write TX_MSB_RIGHT 16 1 read-write RX_MSB_RIGHT 17 1 read-write SIG_LOOPBACK 18 1 read-write INT_RAW 0xC 0x20 RX_TAKE_DATA_INT_RAW 0 1 read-only TX_PUT_DATA_INT_RAW 1 1 read-only RX_WFULL_INT_RAW 2 1 read-only RX_REMPTY_INT_RAW 3 1 read-only TX_WFULL_INT_RAW 4 1 read-only TX_REMPTY_INT_RAW 5 1 read-only RX_HUNG_INT_RAW 6 1 read-only TX_HUNG_INT_RAW 7 1 read-only IN_DONE_INT_RAW 8 1 read-only IN_SUC_EOF_INT_RAW 9 1 read-only IN_ERR_EOF_INT_RAW 10 1 read-only OUT_DONE_INT_RAW 11 1 read-only OUT_EOF_INT_RAW 12 1 read-only IN_DSCR_ERR_INT_RAW 13 1 read-only OUT_DSCR_ERR_INT_RAW 14 1 read-only IN_DSCR_EMPTY_INT_RAW 15 1 read-only OUT_TOTAL_EOF_INT_RAW 16 1 read-only INT_ST 0x10 0x20 RX_TAKE_DATA_INT_ST 0 1 read-only TX_PUT_DATA_INT_ST 1 1 read-only RX_WFULL_INT_ST 2 1 read-only RX_REMPTY_INT_ST 3 1 read-only TX_WFULL_INT_ST 4 1 read-only TX_REMPTY_INT_ST 5 1 read-only RX_HUNG_INT_ST 6 1 read-only TX_HUNG_INT_ST 7 1 read-only IN_DONE_INT_ST 8 1 read-only IN_SUC_EOF_INT_ST 9 1 read-only IN_ERR_EOF_INT_ST 10 1 read-only OUT_DONE_INT_ST 11 1 read-only OUT_EOF_INT_ST 12 1 read-only IN_DSCR_ERR_INT_ST 13 1 read-only OUT_DSCR_ERR_INT_ST 14 1 read-only IN_DSCR_EMPTY_INT_ST 15 1 read-only OUT_TOTAL_EOF_INT_ST 16 1 read-only INT_ENA 0x14 0x20 RX_TAKE_DATA_INT_ENA 0 1 read-write TX_PUT_DATA_INT_ENA 1 1 read-write RX_WFULL_INT_ENA 2 1 read-write RX_REMPTY_INT_ENA 3 1 read-write TX_WFULL_INT_ENA 4 1 read-write TX_REMPTY_INT_ENA 5 1 read-write RX_HUNG_INT_ENA 6 1 read-write TX_HUNG_INT_ENA 7 1 read-write IN_DONE_INT_ENA 8 1 read-write IN_SUC_EOF_INT_ENA 9 1 read-write IN_ERR_EOF_INT_ENA 10 1 read-write OUT_DONE_INT_ENA 11 1 read-write OUT_EOF_INT_ENA 12 1 read-write IN_DSCR_ERR_INT_ENA 13 1 read-write OUT_DSCR_ERR_INT_ENA 14 1 read-write IN_DSCR_EMPTY_INT_ENA 15 1 read-write OUT_TOTAL_EOF_INT_ENA 16 1 read-write INT_CLR 0x18 0x20 TAKE_DATA_INT_CLR 0 1 write-only PUT_DATA_INT_CLR 1 1 write-only RX_WFULL_INT_CLR 2 1 write-only RX_REMPTY_INT_CLR 3 1 write-only TX_WFULL_INT_CLR 4 1 write-only TX_REMPTY_INT_CLR 5 1 write-only RX_HUNG_INT_CLR 6 1 write-only TX_HUNG_INT_CLR 7 1 write-only IN_DONE_INT_CLR 8 1 write-only IN_SUC_EOF_INT_CLR 9 1 write-only IN_ERR_EOF_INT_CLR 10 1 write-only OUT_DONE_INT_CLR 11 1 write-only OUT_EOF_INT_CLR 12 1 write-only IN_DSCR_ERR_INT_CLR 13 1 write-only OUT_DSCR_ERR_INT_CLR 14 1 write-only IN_DSCR_EMPTY_INT_CLR 15 1 write-only OUT_TOTAL_EOF_INT_CLR 16 1 write-only TIMING 0x1C 0x20 TX_BCK_IN_DELAY 0 2 read-write TX_WS_IN_DELAY 2 2 read-write RX_BCK_IN_DELAY 4 2 read-write RX_WS_IN_DELAY 6 2 read-write RX_SD_IN_DELAY 8 2 read-write TX_BCK_OUT_DELAY 10 2 read-write TX_WS_OUT_DELAY 12 2 read-write TX_SD_OUT_DELAY 14 2 read-write RX_WS_OUT_DELAY 16 2 read-write RX_BCK_OUT_DELAY 18 2 read-write TX_DSYNC_SW 20 1 read-write RX_DSYNC_SW 21 1 read-write DATA_ENABLE_DELAY 22 2 read-write TX_BCK_IN_INV 24 1 read-write FIFO_CONF 0x20 0x20 0x00001820 RX_DATA_NUM 0 6 read-write TX_DATA_NUM 6 6 read-write DSCR_EN 12 1 read-write TX_FIFO_MOD 13 3 read-write RX_FIFO_MOD 16 3 read-write TX_FIFO_MOD_FORCE_EN 19 1 read-write RX_FIFO_MOD_FORCE_EN 20 1 read-write RXEOF_NUM 0x24 0x20 0x00000040 RX_EOF_NUM 0 32 read-write CONF_SIGLE_DATA 0x28 0x20 SIGLE_DATA 0 32 read-write CONF_CHAN 0x2C 0x20 TX_CHAN_MOD 0 3 read-write RX_CHAN_MOD 3 2 read-write OUT_LINK 0x30 0x20 OUTLINK_ADDR 0 20 read-write OUTLINK_STOP 28 1 read-write OUTLINK_START 29 1 read-write OUTLINK_RESTART 30 1 read-write OUTLINK_PARK 31 1 read-only IN_LINK 0x34 0x20 INLINK_ADDR 0 20 read-write INLINK_STOP 28 1 read-write INLINK_START 29 1 read-write INLINK_RESTART 30 1 read-write INLINK_PARK 31 1 read-only OUT_EOF_DES_ADDR 0x38 0x20 OUT_EOF_DES_ADDR 0 32 read-only IN_EOF_DES_ADDR 0x3C 0x20 IN_SUC_EOF_DES_ADDR 0 32 read-only OUT_EOF_BFR_DES_ADDR 0x40 0x20 OUT_EOF_BFR_DES_ADDR 0 32 read-only AHB_TEST 0x44 0x20 AHB_TESTMODE 0 3 read-write AHB_TESTADDR 4 2 read-write INLINK_DSCR 0x48 0x20 INLINK_DSCR 0 32 read-only INLINK_DSCR_BF0 0x4C 0x20 INLINK_DSCR_BF0 0 32 read-only INLINK_DSCR_BF1 0x50 0x20 INLINK_DSCR_BF1 0 32 read-only OUTLINK_DSCR 0x54 0x20 OUTLINK_DSCR 0 32 read-only OUTLINK_DSCR_BF0 0x58 0x20 OUTLINK_DSCR_BF0 0 32 read-only OUTLINK_DSCR_BF1 0x5C 0x20 OUTLINK_DSCR_BF1 0 32 read-only LC_CONF 0x60 0x20 0x00000100 IN_RST 0 1 read-write OUT_RST 1 1 read-write AHBM_FIFO_RST 2 1 read-write AHBM_RST 3 1 read-write OUT_LOOP_TEST 4 1 read-write IN_LOOP_TEST 5 1 read-write OUT_AUTO_WRBACK 6 1 read-write OUT_NO_RESTART_CLR 7 1 read-write OUT_EOF_MODE 8 1 read-write OUTDSCR_BURST_EN 9 1 read-write INDSCR_BURST_EN 10 1 read-write OUT_DATA_BURST_EN 11 1 read-write CHECK_OWNER 12 1 read-write MEM_TRANS_EN 13 1 read-write OUTFIFO_PUSH 0x64 0x20 OUTFIFO_WDATA 0 9 read-write OUTFIFO_PUSH 16 1 read-write INFIFO_POP 0x68 0x20 INFIFO_RDATA 0 12 read-only INFIFO_POP 16 1 read-write LC_STATE0 0x6C 0x20 LC_STATE0 0 32 read-only LC_STATE1 0x70 0x20 LC_STATE1 0 32 read-only LC_HUNG_CONF 0x74 0x20 0x00000810 LC_FIFO_TIMEOUT 0 8 read-write LC_FIFO_TIMEOUT_SHIFT 8 3 read-write LC_FIFO_TIMEOUT_ENA 11 1 read-write CVSD_CONF0 0x80 0x20 0x80007FFF CVSD_Y_MAX 0 16 read-write CVSD_Y_MIN 16 16 read-write CVSD_CONF1 0x84 0x20 0x000A0500 CVSD_SIGMA_MAX 0 16 read-write CVSD_SIGMA_MIN 16 16 read-write CVSD_CONF2 0x88 0x20 0x000502A4 CVSD_K 0 3 read-write CVSD_J 3 3 read-write CVSD_BETA 6 10 read-write CVSD_H 16 3 read-write PLC_CONF0 0x8C 0x20 0x08A80339 GOOD_PACK_MAX 0 6 read-write N_ERR_SEG 6 3 read-write SHIFT_RATE 9 3 read-write MAX_SLIDE_SAMPLE 12 8 read-write PACK_LEN_8K 20 5 read-write N_MIN_ERR 25 3 read-write PLC_CONF1 0x90 0x20 0xA0178A05 BAD_CEF_ATTEN_PARA 0 8 read-write BAD_CEF_ATTEN_PARA_SHIFT 8 4 read-write BAD_OLA_WIN2_PARA_SHIFT 12 4 read-write BAD_OLA_WIN2_PARA 16 8 read-write SLIDE_WIN_LEN 24 8 read-write PLC_CONF2 0x94 0x20 0x00000028 CVSD_SEG_MOD 0 2 read-write MIN_PERIOD 2 5 read-write ESCO_CONF0 0x98 0x20 ESCO_EN 0 1 read-write ESCO_CHAN_MOD 1 1 read-write ESCO_CVSD_DEC_PACK_ERR 2 1 read-write ESCO_CVSD_PACK_LEN_8K 3 5 read-write ESCO_CVSD_INF_EN 8 1 read-write CVSD_DEC_START 9 1 read-write CVSD_DEC_RESET 10 1 read-write PLC_EN 11 1 read-write PLC2DMA_EN 12 1 read-write SCO_CONF0 0x9C 0x20 SCO_WITH_I2S_EN 0 1 read-write SCO_NO_I2S_EN 1 1 read-write CVSD_ENC_START 2 1 read-write CVSD_ENC_RESET 3 1 read-write CONF1 0xA0 0x20 0x00000089 TX_PCM_CONF 0 3 read-write TX_PCM_BYPASS 3 1 read-write RX_PCM_CONF 4 3 read-write RX_PCM_BYPASS 7 1 read-write TX_STOP_EN 8 1 read-write TX_ZEROS_RM_EN 9 1 read-write PD_CONF 0xA4 0x20 0x0000000A FIFO_FORCE_PD 0 1 read-write FIFO_FORCE_PU 1 1 read-write PLC_MEM_FORCE_PD 2 1 read-write PLC_MEM_FORCE_PU 3 1 read-write CONF2 0xA8 0x20 CAMERA_EN 0 1 read-write LCD_TX_WRX2_EN 1 1 read-write LCD_TX_SDX2_EN 2 1 read-write DATA_ENABLE_TEST_EN 3 1 read-write DATA_ENABLE 4 1 read-write LCD_EN 5 1 read-write EXT_ADC_START_EN 6 1 read-write INTER_VALID_EN 7 1 read-write CLKM_CONF 0xAC 0x20 0x00000004 CLKM_DIV_NUM 0 8 read-write CLKM_DIV_B 8 6 read-write CLKM_DIV_A 14 6 read-write CLK_EN 20 1 read-write CLKA_ENA 21 1 read-write SAMPLE_RATE_CONF 0xB0 0x20 0x00410186 TX_BCK_DIV_NUM 0 6 read-write RX_BCK_DIV_NUM 6 6 read-write TX_BITS_MOD 12 6 read-write RX_BITS_MOD 18 6 read-write PDM_CONF 0xB4 0x20 0x01550020 TX_PDM_EN 0 1 read-write RX_PDM_EN 1 1 read-write PCM2PDM_CONV_EN 2 1 read-write PDM2PCM_CONV_EN 3 1 read-write TX_PDM_SINC_OSR2 4 4 read-write TX_PDM_PRESCALE 8 8 read-write TX_PDM_HP_IN_SHIFT 16 2 read-write TX_PDM_LP_IN_SHIFT 18 2 read-write TX_PDM_SINC_IN_SHIFT 20 2 read-write TX_PDM_SIGMADELTA_IN_SHIFT 22 2 read-write RX_PDM_SINC_DSR_16_EN 24 1 read-write TX_PDM_HP_BYPASS 25 1 read-write PDM_FREQ_CONF 0xB8 0x20 0x000F01E0 TX_PDM_FS 0 10 read-write TX_PDM_FP 10 10 read-write STATE 0xBC 0x20 0x00000007 TX_IDLE 0 1 read-only TX_FIFO_RESET_BACK 1 1 read-only RX_FIFO_RESET_BACK 2 1 read-only DATE 0xFC 0x20 0x01604201 I2SDATE 0 32 read-write I2S1 I2S (Inter-IC Sound) Controller 0x3FF6D000 I2S1 33 IO_MUX Input/Output Multiplexer IO_MUX 0x3FF49000 0x0 0x94 registers PIN_CTRL 0x0 0x20 CLK1 If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. 0 4 read-write CLK2 If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. 4 4 read-write CLK3 If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. 8 4 read-write GPIO36 0x4 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO37 0x8 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO38 0xC 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO39 0x10 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO34 0x14 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO35 0x18 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO32 0x1C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO33 0x20 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO25 0x24 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO26 0x28 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO27 0x2C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO14 0x30 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO12 0x34 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO13 0x38 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO15 0x3C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO2 0x40 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO0 0x44 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO4 0x48 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO16 0x4C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO17 0x50 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO9 0x54 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO10 0x58 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO11 0x5C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO6 0x60 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO7 0x64 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO8 0x68 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO5 0x6C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO18 0x70 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO19 0x74 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO20 0x78 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO21 0x7C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO22 0x80 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO3 0x84 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO1 0x88 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO23 0x8C 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write GPIO24 0x90 0x20 MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. 1 1 read-write MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet. 10 2 read-write MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc. 12 3 read-write LEDC LED Control PWM (Pulse Width Modulation) LEDC 0x3FF59000 0x0 0x198 registers LEDC 43 TIMER1 56 TIMER2 57 8 0x14 0-7 HSCH%s_CONF0 0x0 0x20 TIMER_SEL There are four high speed timers the two bits are used to select one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3. 0 2 read-write SIG_OUT_EN This is the output enable control bit for high speed channel0 2 1 read-write IDLE_LV This bit is used to control the output value when high speed channel0 is off. 3 1 read-write 8 0x14 0-7 HSCH%s_HPOINT 0x4 0x20 HPOINT The output value changes to high when htimerx(x=[0 3]) selected by high speed channel0 has reached reg_hpoint_hsch0[19:0] 0 20 read-write 8 0x14 0-7 HSCH%s_DUTY 0x8 0x20 DUTY This register represents the current duty of the output signal for high speed channel0. 0 25 read-write 8 0x14 0-7 HSCH%s_CONF1 0xC 0x20 0x40000000 DUTY_SCALE This register controls the increase or decrease step scale for high speed channel0. 0 10 read-write DUTY_CYCLE This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0. 10 10 read-write DUTY_NUM This register is used to control the num of increased or decreased times for high speed channel0. 20 10 read-write DUTY_INC This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0. 30 1 read-write DUTY_START When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware. 31 1 read-write 8 0x14 0-7 HSCH%s_DUTY_R 0x10 0x20 DUTY_R This register represents the current duty cycle of the output signal for high-speed channel %s 0 25 read-only 8 0x14 0-7 LSCH%s_CONF0 0xA0 0x20 TIMER_SEL There are four low speed timers the two bits are used to select one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3. 0 2 read-write SIG_OUT_EN This is the output enable control bit for low speed channel0. 2 1 read-write IDLE_LV This bit is used to control the output value when low speed channel0 is off. 3 1 read-write PARA_UP This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0. 4 1 read-write 8 0x14 0-7 LSCH%s_HPOINT 0xA4 0x20 HPOINT The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel0 has reached reg_hpoint_lsch0[19:0] 0 20 read-write 8 0x14 0-7 LSCH%s_DUTY 0xA8 0x20 read-write DUTY This register represents the current duty of the output signal for low speed channel0. 0 25 read-write 8 0x14 0-7 LSCH%s_CONF1 0xAC 0x20 0x40000000 DUTY_SCALE This register controls the increase or decrease step scale for low speed channel0. 0 10 read-write DUTY_CYCLE This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0. 10 10 read-write DUTY_NUM This register is used to control the num of increased or decreased times for low speed channel6. 20 10 read-write DUTY_INC This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6. 30 1 read-write DUTY_START When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware. 31 1 read-write 8 0x14 0-7 LSCH%s_DUTY_R 0xB0 0x20 DUTY_R This register represents the current duty cycle of the output signal for low-speed channel %s 0 25 read-only 4 0x8 0-3 HSTIMER%s_CONF 0x140 0x20 0x01000000 DUTY_RES This register controls the range of the counter in high speed timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20. 0 5 read-write DIV_NUM This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part. 5 18 read-write PAUSE This bit is used to pause the counter in high speed timer0 23 1 read-write RST This bit is used to reset high speed timer0 the counter will be 0 after reset. 24 1 read-write TICK_SEL This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk 0:ref_tick 25 1 read-write LIM 31 5 read-write 4 0x8 0-3 HSTIMER%s_VALUE 0x144 0x20 CNT software can read this register to get the current counter value in high speed timer0 0 20 read-only 4 0x8 0-3 LSTIMER%s_CONF 0x160 0x20 0x01000000 DUTY_RES This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20. 0 5 read-write DIV_NUM This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part. 5 18 read-write PAUSE This bit is used to pause the counter in low speed timer0. 23 1 read-write RST This bit is used to reset low speed timer0 the counter will be 0 after reset. 24 1 read-write TICK_SEL This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk 0:ref_tick 25 1 read-write PARA_UP Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim. 26 1 read-write LIM 31 5 read-write 4 0x8 0-3 LSTIMER%s_VALUE 0x164 0x20 CNT software can read this register to get the current counter value in low speed timer0. 0 20 read-only INT_RAW 0x180 0x20 HSTIMER0_OVF_INT_RAW The interrupt raw bit for high speed channel0 counter overflow. 0 1 read-only HSTIMER1_OVF_INT_RAW The interrupt raw bit for high speed channel1 counter overflow. 1 1 read-only HSTIMER2_OVF_INT_RAW The interrupt raw bit for high speed channel2 counter overflow. 2 1 read-only HSTIMER3_OVF_INT_RAW The interrupt raw bit for high speed channel3 counter overflow. 3 1 read-only LSTIMER0_OVF_INT_RAW The interrupt raw bit for low speed channel0 counter overflow. 4 1 read-only LSTIMER1_OVF_INT_RAW The interrupt raw bit for low speed channel1 counter overflow. 5 1 read-only LSTIMER2_OVF_INT_RAW The interrupt raw bit for low speed channel2 counter overflow. 6 1 read-only LSTIMER3_OVF_INT_RAW The interrupt raw bit for low speed channel3 counter overflow. 7 1 read-only DUTY_CHNG_END_HSCH0_INT_RAW The interrupt raw bit for high speed channel 0 duty change done. 8 1 read-only DUTY_CHNG_END_HSCH1_INT_RAW The interrupt raw bit for high speed channel 1 duty change done. 9 1 read-only DUTY_CHNG_END_HSCH2_INT_RAW The interrupt raw bit for high speed channel 2 duty change done. 10 1 read-only DUTY_CHNG_END_HSCH3_INT_RAW The interrupt raw bit for high speed channel 3 duty change done. 11 1 read-only DUTY_CHNG_END_HSCH4_INT_RAW The interrupt raw bit for high speed channel 4 duty change done. 12 1 read-only DUTY_CHNG_END_HSCH5_INT_RAW The interrupt raw bit for high speed channel 5 duty change done. 13 1 read-only DUTY_CHNG_END_HSCH6_INT_RAW The interrupt raw bit for high speed channel 6 duty change done. 14 1 read-only DUTY_CHNG_END_HSCH7_INT_RAW The interrupt raw bit for high speed channel 7 duty change done. 15 1 read-only DUTY_CHNG_END_LSCH0_INT_RAW The interrupt raw bit for low speed channel 0 duty change done. 16 1 read-only DUTY_CHNG_END_LSCH1_INT_RAW The interrupt raw bit for low speed channel 1 duty change done. 17 1 read-only DUTY_CHNG_END_LSCH2_INT_RAW The interrupt raw bit for low speed channel 2 duty change done. 18 1 read-only DUTY_CHNG_END_LSCH3_INT_RAW The interrupt raw bit for low speed channel 3 duty change done. 19 1 read-only DUTY_CHNG_END_LSCH4_INT_RAW The interrupt raw bit for low speed channel 4 duty change done. 20 1 read-only DUTY_CHNG_END_LSCH5_INT_RAW The interrupt raw bit for low speed channel 5 duty change done. 21 1 read-only DUTY_CHNG_END_LSCH6_INT_RAW The interrupt raw bit for low speed channel 6 duty change done. 22 1 read-only DUTY_CHNG_END_LSCH7_INT_RAW The interrupt raw bit for low speed channel 7 duty change done. 23 1 read-only INT_ST 0x184 0x20 HSTIMER0_OVF_INT_ST The interrupt status bit for high speed channel0 counter overflow event. 0 1 read-only HSTIMER1_OVF_INT_ST The interrupt status bit for high speed channel1 counter overflow event. 1 1 read-only HSTIMER2_OVF_INT_ST The interrupt status bit for high speed channel2 counter overflow event. 2 1 read-only HSTIMER3_OVF_INT_ST The interrupt status bit for high speed channel3 counter overflow event. 3 1 read-only LSTIMER0_OVF_INT_ST The interrupt status bit for low speed channel0 counter overflow event. 4 1 read-only LSTIMER1_OVF_INT_ST The interrupt status bit for low speed channel1 counter overflow event. 5 1 read-only LSTIMER2_OVF_INT_ST The interrupt status bit for low speed channel2 counter overflow event. 6 1 read-only LSTIMER3_OVF_INT_ST The interrupt status bit for low speed channel3 counter overflow event. 7 1 read-only DUTY_CHNG_END_HSCH0_INT_ST The interrupt status bit for high speed channel 0 duty change done event. 8 1 read-only DUTY_CHNG_END_HSCH1_INT_ST The interrupt status bit for high speed channel 1 duty change done event. 9 1 read-only DUTY_CHNG_END_HSCH2_INT_ST The interrupt status bit for high speed channel 2 duty change done event. 10 1 read-only DUTY_CHNG_END_HSCH3_INT_ST The interrupt status bit for high speed channel 3 duty change done event. 11 1 read-only DUTY_CHNG_END_HSCH4_INT_ST The interrupt status bit for high speed channel 4 duty change done event. 12 1 read-only DUTY_CHNG_END_HSCH5_INT_ST The interrupt status bit for high speed channel 5 duty change done event. 13 1 read-only DUTY_CHNG_END_HSCH6_INT_ST The interrupt status bit for high speed channel 6 duty change done event. 14 1 read-only DUTY_CHNG_END_HSCH7_INT_ST The interrupt status bit for high speed channel 7 duty change done event. 15 1 read-only DUTY_CHNG_END_LSCH0_INT_ST The interrupt status bit for low speed channel 0 duty change done event. 16 1 read-only DUTY_CHNG_END_LSCH1_INT_ST The interrupt status bit for low speed channel 1 duty change done event. 17 1 read-only DUTY_CHNG_END_LSCH2_INT_ST The interrupt status bit for low speed channel 2 duty change done event. 18 1 read-only DUTY_CHNG_END_LSCH3_INT_ST The interrupt status bit for low speed channel 3 duty change done event. 19 1 read-only DUTY_CHNG_END_LSCH4_INT_ST The interrupt status bit for low speed channel 4 duty change done event. 20 1 read-only DUTY_CHNG_END_LSCH5_INT_ST The interrupt status bit for low speed channel 5 duty change done event. 21 1 read-only DUTY_CHNG_END_LSCH6_INT_ST The interrupt status bit for low speed channel 6 duty change done event. 22 1 read-only DUTY_CHNG_END_LSCH7_INT_ST The interrupt status bit for low speed channel 7 duty change done event 23 1 read-only INT_ENA 0x188 0x20 HSTIMER0_OVF_INT_ENA The interrupt enable bit for high speed channel0 counter overflow interrupt. 0 1 read-write HSTIMER1_OVF_INT_ENA The interrupt enable bit for high speed channel1 counter overflow interrupt. 1 1 read-write HSTIMER2_OVF_INT_ENA The interrupt enable bit for high speed channel2 counter overflow interrupt. 2 1 read-write HSTIMER3_OVF_INT_ENA The interrupt enable bit for high speed channel3 counter overflow interrupt. 3 1 read-write LSTIMER0_OVF_INT_ENA The interrupt enable bit for low speed channel0 counter overflow interrupt. 4 1 read-write LSTIMER1_OVF_INT_ENA The interrupt enable bit for low speed channel1 counter overflow interrupt. 5 1 read-write LSTIMER2_OVF_INT_ENA The interrupt enable bit for low speed channel2 counter overflow interrupt. 6 1 read-write LSTIMER3_OVF_INT_ENA The interrupt enable bit for low speed channel3 counter overflow interrupt. 7 1 read-write DUTY_CHNG_END_HSCH0_INT_ENA The interrupt enable bit for high speed channel 0 duty change done interrupt. 8 1 read-write DUTY_CHNG_END_HSCH1_INT_ENA The interrupt enable bit for high speed channel 1 duty change done interrupt. 9 1 read-write DUTY_CHNG_END_HSCH2_INT_ENA The interrupt enable bit for high speed channel 2 duty change done interrupt. 10 1 read-write DUTY_CHNG_END_HSCH3_INT_ENA The interrupt enable bit for high speed channel 3 duty change done interrupt. 11 1 read-write DUTY_CHNG_END_HSCH4_INT_ENA The interrupt enable bit for high speed channel 4 duty change done interrupt. 12 1 read-write DUTY_CHNG_END_HSCH5_INT_ENA The interrupt enable bit for high speed channel 5 duty change done interrupt. 13 1 read-write DUTY_CHNG_END_HSCH6_INT_ENA The interrupt enable bit for high speed channel 6 duty change done interrupt. 14 1 read-write DUTY_CHNG_END_HSCH7_INT_ENA The interrupt enable bit for high speed channel 7 duty change done interrupt. 15 1 read-write DUTY_CHNG_END_LSCH0_INT_ENA The interrupt enable bit for low speed channel 0 duty change done interrupt. 16 1 read-write DUTY_CHNG_END_LSCH1_INT_ENA The interrupt enable bit for low speed channel 1 duty change done interrupt. 17 1 read-write DUTY_CHNG_END_LSCH2_INT_ENA The interrupt enable bit for low speed channel 2 duty change done interrupt. 18 1 read-write DUTY_CHNG_END_LSCH3_INT_ENA The interrupt enable bit for low speed channel 3 duty change done interrupt. 19 1 read-write DUTY_CHNG_END_LSCH4_INT_ENA The interrupt enable bit for low speed channel 4 duty change done interrupt. 20 1 read-write DUTY_CHNG_END_LSCH5_INT_ENA The interrupt enable bit for low speed channel 5 duty change done interrupt. 21 1 read-write DUTY_CHNG_END_LSCH6_INT_ENA The interrupt enable bit for low speed channel 6 duty change done interrupt. 22 1 read-write DUTY_CHNG_END_LSCH7_INT_ENA The interrupt enable bit for low speed channel 7 duty change done interrupt. 23 1 read-write INT_CLR 0x18C 0x20 HSTIMER0_OVF_INT_CLR Set this bit to clear high speed channel0 counter overflow interrupt. 0 1 write-only HSTIMER1_OVF_INT_CLR Set this bit to clear high speed channel1 counter overflow interrupt. 1 1 write-only HSTIMER2_OVF_INT_CLR Set this bit to clear high speed channel2 counter overflow interrupt. 2 1 write-only HSTIMER3_OVF_INT_CLR Set this bit to clear high speed channel3 counter overflow interrupt. 3 1 write-only LSTIMER0_OVF_INT_CLR Set this bit to clear low speed channel0 counter overflow interrupt. 4 1 write-only LSTIMER1_OVF_INT_CLR Set this bit to clear low speed channel1 counter overflow interrupt. 5 1 write-only LSTIMER2_OVF_INT_CLR Set this bit to clear low speed channel2 counter overflow interrupt. 6 1 write-only LSTIMER3_OVF_INT_CLR Set this bit to clear low speed channel3 counter overflow interrupt. 7 1 write-only DUTY_CHNG_END_HSCH0_INT_CLR Set this bit to clear high speed channel 0 duty change done interrupt. 8 1 write-only DUTY_CHNG_END_HSCH1_INT_CLR Set this bit to clear high speed channel 1 duty change done interrupt. 9 1 write-only DUTY_CHNG_END_HSCH2_INT_CLR Set this bit to clear high speed channel 2 duty change done interrupt. 10 1 write-only DUTY_CHNG_END_HSCH3_INT_CLR Set this bit to clear high speed channel 3 duty change done interrupt. 11 1 write-only DUTY_CHNG_END_HSCH4_INT_CLR Set this bit to clear high speed channel 4 duty change done interrupt. 12 1 write-only DUTY_CHNG_END_HSCH5_INT_CLR Set this bit to clear high speed channel 5 duty change done interrupt. 13 1 write-only DUTY_CHNG_END_HSCH6_INT_CLR Set this bit to clear high speed channel 6 duty change done interrupt. 14 1 write-only DUTY_CHNG_END_HSCH7_INT_CLR Set this bit to clear high speed channel 7 duty change done interrupt. 15 1 write-only DUTY_CHNG_END_LSCH0_INT_CLR Set this bit to clear low speed channel 0 duty change done interrupt. 16 1 write-only DUTY_CHNG_END_LSCH1_INT_CLR Set this bit to clear low speed channel 1 duty change done interrupt. 17 1 write-only DUTY_CHNG_END_LSCH2_INT_CLR Set this bit to clear low speed channel 2 duty change done interrupt. 18 1 write-only DUTY_CHNG_END_LSCH3_INT_CLR Set this bit to clear low speed channel 3 duty change done interrupt. 19 1 write-only DUTY_CHNG_END_LSCH4_INT_CLR Set this bit to clear low speed channel 4 duty change done interrupt. 20 1 write-only DUTY_CHNG_END_LSCH5_INT_CLR Set this bit to clear low speed channel 5 duty change done interrupt. 21 1 write-only DUTY_CHNG_END_LSCH6_INT_CLR Set this bit to clear low speed channel 6 duty change done interrupt. 22 1 write-only DUTY_CHNG_END_LSCH7_INT_CLR Set this bit to clear low speed channel 7 duty change done interrupt. 23 1 write-only CONF 0x190 0x20 APB_CLK_SEL This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz 0 1 read-write DATE 0x1FC 0x20 0x16031700 DATE This register represents the version . 0 32 read-write PWM0 Motor Control Pulse-Width Modulation MCPWM 0x3FF5E000 0x0 0x128 registers PWM0 39 CLK_CFG 0x0 0x20 CLK_PRESCALE 0 8 read-write TIMER0_CFG0 0x4 0x20 0x0000FF00 TIMER0_PRESCALE 0 8 read-write TIMER0_PERIOD 8 16 read-write TIMER0_PERIOD_UPMETHOD 24 2 read-write TIMER0_CFG1 0x8 0x20 TIMER0_START 0 3 read-write TIMER0_MOD 3 2 read-write TIMER0_SYNC 0xC 0x20 TIMER0_SYNCI_EN 0 1 read-write SW 1 1 read-write TIMER0_SYNCO_SEL 2 2 read-write TIMER0_PHASE 4 16 read-write TIMER0_PHASE_DIRECTION 20 1 read-write TIMER0_STATUS 0x10 0x20 TIMER0_VALUE 0 16 read-only TIMER0_DIRECTION 16 1 read-only TIMER1_CFG0 0x14 0x20 0x0000FF00 TIMER1_PRESCALE 0 8 read-write TIMER1_PERIOD 8 16 read-write TIMER1_PERIOD_UPMETHOD 24 2 read-write TIMER1_CFG1 0x18 0x20 TIMER1_START 0 3 read-write TIMER1_MOD 3 2 read-write TIMER1_SYNC 0x1C 0x20 TIMER1_SYNCI_EN 0 1 read-write SW 1 1 read-write TIMER1_SYNCO_SEL 2 2 read-write TIMER1_PHASE 4 16 read-write TIMER1_PHASE_DIRECTION 20 1 read-write TIMER1_STATUS 0x20 0x20 TIMER1_VALUE 0 16 read-only TIMER1_DIRECTION 16 1 read-only TIMER2_CFG0 0x24 0x20 0x0000FF00 TIMER2_PRESCALE 0 8 read-write TIMER2_PERIOD 8 16 read-write TIMER2_PERIOD_UPMETHOD 24 2 read-write TIMER2_CFG1 0x28 0x20 TIMER2_START 0 3 read-write TIMER2_MOD 3 2 read-write TIMER2_SYNC 0x2C 0x20 TIMER2_SYNCI_EN 0 1 read-write SW 1 1 read-write TIMER2_SYNCO_SEL 2 2 read-write TIMER2_PHASE 4 16 read-write TIMER2_PHASE_DIRECTION 20 1 read-write TIMER2_STATUS 0x30 0x20 TIMER2_VALUE 0 16 read-only TIMER2_DIRECTION 16 1 read-only TIMER_SYNCI_CFG 0x34 0x20 TIMER0_SYNCISEL 0 3 read-write TIMER1_SYNCISEL 3 3 read-write TIMER2_SYNCISEL 6 3 read-write EXTERNAL_SYNCI0_INVERT 9 1 read-write EXTERNAL_SYNCI1_INVERT 10 1 read-write EXTERNAL_SYNCI2_INVERT 11 1 read-write OPERATOR_TIMERSEL 0x38 0x20 OPERATOR0_TIMERSEL 0 2 read-write OPERATOR1_TIMERSEL 2 2 read-write OPERATOR2_TIMERSEL 4 2 read-write GEN0_STMP_CFG 0x3C 0x20 GEN0_A_UPMETHOD 0 4 read-write GEN0_B_UPMETHOD 4 4 read-write GEN0_A_SHDW_FULL 8 1 read-write GEN0_B_SHDW_FULL 9 1 read-write GEN0_TSTMP_A 0x40 0x20 GEN0_A 0 16 read-write GEN0_TSTMP_B 0x44 0x20 GEN0_B 0 16 read-write GEN0_CFG0 0x48 0x20 GEN0_CFG_UPMETHOD 0 4 read-write GEN0_T0_SEL 4 3 read-write GEN0_T1_SEL 7 3 read-write GEN0_FORCE 0x4C 0x20 0x00000020 GEN0_CNTUFORCE_UPMETHOD 0 6 read-write GEN0_A_CNTUFORCE_MODE 6 2 read-write GEN0_B_CNTUFORCE_MODE 8 2 read-write GEN0_A_NCIFORCE 10 1 read-write GEN0_A_NCIFORCE_MODE 11 2 read-write GEN0_B_NCIFORCE 13 1 read-write GEN0_B_NCIFORCE_MODE 14 2 read-write GEN0_A 0x50 0x20 UTEZ 0 2 read-write UTEP 2 2 read-write UTEA 4 2 read-write UTEB 6 2 read-write UT0 8 2 read-write UT1 10 2 read-write DTEZ 12 2 read-write DTEP 14 2 read-write DTEA 16 2 read-write DTEB 18 2 read-write DT0 20 2 read-write DT1 22 2 read-write GEN0_B 0x54 0x20 UTEZ 0 2 read-write UTEP 2 2 read-write UTEA 4 2 read-write UTEB 6 2 read-write UT0 8 2 read-write UT1 10 2 read-write DTEZ 12 2 read-write DTEP 14 2 read-write DTEA 16 2 read-write DTEB 18 2 read-write DT0 20 2 read-write DT1 22 2 read-write DT0_CFG 0x58 0x20 0x00018000 DT0_FED_UPMETHOD 0 4 read-write DT0_RED_UPMETHOD 4 4 read-write DT0_DEB_MODE 8 1 read-write DT0_A_OUTSWAP 9 1 read-write DT0_B_OUTSWAP 10 1 read-write DT0_RED_INSEL 11 1 read-write DT0_FED_INSEL 12 1 read-write DT0_RED_OUTINVERT 13 1 read-write DT0_FED_OUTINVERT 14 1 read-write DT0_A_OUTBYPASS 15 1 read-write DT0_B_OUTBYPASS 16 1 read-write DT0_CLK_SEL 17 1 read-write DT0_FED_CFG 0x5C 0x20 DT0_FED 0 16 read-write DT0_RED_CFG 0x60 0x20 DT0_RED 0 16 read-write CARRIER0_CFG 0x64 0x20 CARRIER0_EN 0 1 read-write CARRIER0_PRESCALE 1 4 read-write CARRIER0_DUTY 5 3 read-write CARRIER0_OSHTWTH 8 4 read-write CARRIER0_OUT_INVERT 12 1 read-write CARRIER0_IN_INVERT 13 1 read-write FH0_CFG0 0x68 0x20 FH0_SW_CBC 0 1 read-write FH0_F2_CBC 1 1 read-write FH0_F1_CBC 2 1 read-write FH0_F0_CBC 3 1 read-write FH0_SW_OST 4 1 read-write FH0_F2_OST 5 1 read-write FH0_F1_OST 6 1 read-write FH0_F0_OST 7 1 read-write FH0_A_CBC_D 8 2 read-write FH0_A_CBC_U 10 2 read-write FH0_A_OST_D 12 2 read-write FH0_A_OST_U 14 2 read-write FH0_B_CBC_D 16 2 read-write FH0_B_CBC_U 18 2 read-write FH0_B_OST_D 20 2 read-write FH0_B_OST_U 22 2 read-write FH0_CFG1 0x6C 0x20 FH0_CLR_OST 0 1 read-write FH0_CBCPULSE 1 2 read-write FH0_FORCE_CBC 3 1 read-write FH0_FORCE_OST 4 1 read-write FH0_STATUS 0x70 0x20 FH0_CBC_ON 0 1 read-only FH0_OST_ON 1 1 read-only GEN1_STMP_CFG 0x74 0x20 GEN1_A_UPMETHOD 0 4 read-write GEN1_B_UPMETHOD 4 4 read-write GEN1_A_SHDW_FULL 8 1 read-write GEN1_B_SHDW_FULL 9 1 read-write GEN1_TSTMP_A 0x78 0x20 GEN1_A 0 16 read-write GEN1_TSTMP_B 0x7C 0x20 GEN1_B 0 16 read-write GEN1_CFG0 0x80 0x20 GEN1_CFG_UPMETHOD 0 4 read-write GEN1_T0_SEL 4 3 read-write GEN1_T1_SEL 7 3 read-write GEN1_FORCE 0x84 0x20 0x00000020 GEN1_CNTUFORCE_UPMETHOD 0 6 read-write GEN1_A_CNTUFORCE_MODE 6 2 read-write GEN1_B_CNTUFORCE_MODE 8 2 read-write GEN1_A_NCIFORCE 10 1 read-write GEN1_A_NCIFORCE_MODE 11 2 read-write GEN1_B_NCIFORCE 13 1 read-write GEN1_B_NCIFORCE_MODE 14 2 read-write GEN1_A 0x88 0x20 UTEZ 0 2 read-write UTEP 2 2 read-write UTEA 4 2 read-write UTEB 6 2 read-write UT0 8 2 read-write UT1 10 2 read-write DTEZ 12 2 read-write DTEP 14 2 read-write DTEA 16 2 read-write DTEB 18 2 read-write DT0 20 2 read-write DT1 22 2 read-write GEN1_B 0x8C 0x20 UTEZ 0 2 read-write UTEP 2 2 read-write UTEA 4 2 read-write UTEB 6 2 read-write UT0 8 2 read-write UT1 10 2 read-write DTEZ 12 2 read-write DTEP 14 2 read-write DTEA 16 2 read-write DTEB 18 2 read-write DT0 20 2 read-write DT1 22 2 read-write DT1_CFG 0x90 0x20 0x00018000 DT1_FED_UPMETHOD 0 4 read-write DT1_RED_UPMETHOD 4 4 read-write DT1_DEB_MODE 8 1 read-write DT1_A_OUTSWAP 9 1 read-write DT1_B_OUTSWAP 10 1 read-write DT1_RED_INSEL 11 1 read-write DT1_FED_INSEL 12 1 read-write DT1_RED_OUTINVERT 13 1 read-write DT1_FED_OUTINVERT 14 1 read-write DT1_A_OUTBYPASS 15 1 read-write DT1_B_OUTBYPASS 16 1 read-write DT1_CLK_SEL 17 1 read-write DT1_FED_CFG 0x94 0x20 DT1_FED 0 16 read-write DT1_RED_CFG 0x98 0x20 DT1_RED 0 16 read-write CARRIER1_CFG 0x9C 0x20 CARRIER1_EN 0 1 read-write CARRIER1_PRESCALE 1 4 read-write CARRIER1_DUTY 5 3 read-write CARRIER1_OSHTWTH 8 4 read-write CARRIER1_OUT_INVERT 12 1 read-write CARRIER1_IN_INVERT 13 1 read-write FH1_CFG0 0xA0 0x20 FH1_SW_CBC 0 1 read-write FH1_F2_CBC 1 1 read-write FH1_F1_CBC 2 1 read-write FH1_F0_CBC 3 1 read-write FH1_SW_OST 4 1 read-write FH1_F2_OST 5 1 read-write FH1_F1_OST 6 1 read-write FH1_F0_OST 7 1 read-write FH1_A_CBC_D 8 2 read-write FH1_A_CBC_U 10 2 read-write FH1_A_OST_D 12 2 read-write FH1_A_OST_U 14 2 read-write FH1_B_CBC_D 16 2 read-write FH1_B_CBC_U 18 2 read-write FH1_B_OST_D 20 2 read-write FH1_B_OST_U 22 2 read-write FH1_CFG1 0xA4 0x20 FH1_CLR_OST 0 1 read-write FH1_CBCPULSE 1 2 read-write FH1_FORCE_CBC 3 1 read-write FH1_FORCE_OST 4 1 read-write FH1_STATUS 0xA8 0x20 FH1_CBC_ON 0 1 read-only FH1_OST_ON 1 1 read-only GEN2_STMP_CFG 0xAC 0x20 GEN2_A_UPMETHOD 0 4 read-write GEN2_B_UPMETHOD 4 4 read-write GEN2_A_SHDW_FULL 8 1 read-write GEN2_B_SHDW_FULL 9 1 read-write GEN2_TSTMP_A 0xB0 0x20 GEN2_A 0 16 read-write GEN2_TSTMP_B 0xB4 0x20 GEN2_B 0 16 read-write GEN2_CFG0 0xB8 0x20 GEN2_CFG_UPMETHOD 0 4 read-write GEN2_T0_SEL 4 3 read-write GEN2_T1_SEL 7 3 read-write GEN2_FORCE 0xBC 0x20 0x00000020 GEN2_CNTUFORCE_UPMETHOD 0 6 read-write GEN2_A_CNTUFORCE_MODE 6 2 read-write GEN2_B_CNTUFORCE_MODE 8 2 read-write GEN2_A_NCIFORCE 10 1 read-write GEN2_A_NCIFORCE_MODE 11 2 read-write GEN2_B_NCIFORCE 13 1 read-write GEN2_B_NCIFORCE_MODE 14 2 read-write GEN2_A 0xC0 0x20 UTEZ 0 2 read-write UTEP 2 2 read-write UTEA 4 2 read-write UTEB 6 2 read-write UT0 8 2 read-write UT1 10 2 read-write DTEZ 12 2 read-write DTEP 14 2 read-write DTEA 16 2 read-write DTEB 18 2 read-write DT0 20 2 read-write DT1 22 2 read-write GEN2_B 0xC4 0x20 UTEZ 0 2 read-write UTEP 2 2 read-write UTEA 4 2 read-write UTEB 6 2 read-write UT0 8 2 read-write UT1 10 2 read-write DTEZ 12 2 read-write DTEP 14 2 read-write DTEA 16 2 read-write DTEB 18 2 read-write DT0 20 2 read-write DT1 22 2 read-write DT2_CFG 0xC8 0x20 0x00018000 DT2_FED_UPMETHOD 0 4 read-write DT2_RED_UPMETHOD 4 4 read-write DT2_DEB_MODE 8 1 read-write DT2_A_OUTSWAP 9 1 read-write DT2_B_OUTSWAP 10 1 read-write DT2_RED_INSEL 11 1 read-write DT2_FED_INSEL 12 1 read-write DT2_RED_OUTINVERT 13 1 read-write DT2_FED_OUTINVERT 14 1 read-write DT2_A_OUTBYPASS 15 1 read-write DT2_B_OUTBYPASS 16 1 read-write DT2_CLK_SEL 17 1 read-write DT2_FED_CFG 0xCC 0x20 DT2_FED 0 16 read-write DT2_RED_CFG 0xD0 0x20 DT2_RED 0 16 read-write CARRIER2_CFG 0xD4 0x20 CARRIER2_EN 0 1 read-write CARRIER2_PRESCALE 1 4 read-write CARRIER2_DUTY 5 3 read-write CARRIER2_OSHTWTH 8 4 read-write CARRIER2_OUT_INVERT 12 1 read-write CARRIER2_IN_INVERT 13 1 read-write FH2_CFG0 0xD8 0x20 FH2_SW_CBC 0 1 read-write FH2_F2_CBC 1 1 read-write FH2_F1_CBC 2 1 read-write FH2_F0_CBC 3 1 read-write FH2_SW_OST 4 1 read-write FH2_F2_OST 5 1 read-write FH2_F1_OST 6 1 read-write FH2_F0_OST 7 1 read-write FH2_A_CBC_D 8 2 read-write FH2_A_CBC_U 10 2 read-write FH2_A_OST_D 12 2 read-write FH2_A_OST_U 14 2 read-write FH2_B_CBC_D 16 2 read-write FH2_B_CBC_U 18 2 read-write FH2_B_OST_D 20 2 read-write FH2_B_OST_U 22 2 read-write FH2_CFG1 0xDC 0x20 FH2_CLR_OST 0 1 read-write FH2_CBCPULSE 1 2 read-write FH2_FORCE_CBC 3 1 read-write FH2_FORCE_OST 4 1 read-write FH2_STATUS 0xE0 0x20 FH2_CBC_ON 0 1 read-only FH2_OST_ON 1 1 read-only FAULT_DETECT 0xE4 0x20 F0_EN 0 1 read-write F1_EN 1 1 read-write F2_EN 2 1 read-write F0_POLE 3 1 read-write F1_POLE 4 1 read-write F2_POLE 5 1 read-write EVENT_F0 6 1 read-only EVENT_F1 7 1 read-only EVENT_F2 8 1 read-only CAP_TIMER_CFG 0xE8 0x20 CAP_TIMER_EN 0 1 read-write CAP_SYNCI_EN 1 1 read-write CAP_SYNCI_SEL 2 3 read-write CAP_SYNC_SW 5 1 write-only CAP_TIMER_PHASE 0xEC 0x20 CAP_TIMER_PHASE 0 32 read-write CAP_CH0_CFG 0xF0 0x20 CAP0_EN 0 1 read-write CAP0_MODE 1 2 read-write CAP0_PRESCALE 3 8 read-write CAP0_IN_INVERT 11 1 read-write CAP0_SW 12 1 write-only CAP_CH1_CFG 0xF4 0x20 CAP1_EN 0 1 read-write CAP1_MODE 1 2 read-write CAP1_PRESCALE 3 8 read-write CAP1_IN_INVERT 11 1 read-write CAP1_SW 12 1 write-only CAP_CH2_CFG 0xF8 0x20 CAP2_EN 0 1 read-write CAP2_MODE 1 2 read-write CAP2_PRESCALE 3 8 read-write CAP2_IN_INVERT 11 1 read-write CAP2_SW 12 1 write-only CAP_CH0 0xFC 0x20 CAP0_VALUE 0 32 read-only CAP_CH1 0x100 0x20 CAP1_VALUE 0 32 read-only CAP_CH2 0x104 0x20 CAP2_VALUE 0 32 read-only CAP_STATUS 0x108 0x20 CAP0_EDGE 0 1 read-only CAP1_EDGE 1 1 read-only CAP2_EDGE 2 1 read-only UPDATE_CFG 0x10C 0x20 0x00000055 GLOBAL_UP_EN 0 1 read-write GLOBAL_FORCE_UP 1 1 read-write OP0_UP_EN 2 1 read-write OP0_FORCE_UP 3 1 read-write OP1_UP_EN 4 1 read-write OP1_FORCE_UP 5 1 read-write OP2_UP_EN 6 1 read-write OP2_FORCE_UP 7 1 read-write INT_ENA 0x110 0x20 TIMER0_STOP_INT_ENA 0 1 read-write TIMER1_STOP_INT_ENA 1 1 read-write TIMER2_STOP_INT_ENA 2 1 read-write TIMER0_TEZ_INT_ENA 3 1 read-write TIMER1_TEZ_INT_ENA 4 1 read-write TIMER2_TEZ_INT_ENA 5 1 read-write TIMER0_TEP_INT_ENA 6 1 read-write TIMER1_TEP_INT_ENA 7 1 read-write TIMER2_TEP_INT_ENA 8 1 read-write FAULT0_INT_ENA 9 1 read-write FAULT1_INT_ENA 10 1 read-write FAULT2_INT_ENA 11 1 read-write FAULT0_CLR_INT_ENA 12 1 read-write FAULT1_CLR_INT_ENA 13 1 read-write FAULT2_CLR_INT_ENA 14 1 read-write OP0_TEA_INT_ENA 15 1 read-write OP1_TEA_INT_ENA 16 1 read-write OP2_TEA_INT_ENA 17 1 read-write OP0_TEB_INT_ENA 18 1 read-write OP1_TEB_INT_ENA 19 1 read-write OP2_TEB_INT_ENA 20 1 read-write FH0_CBC_INT_ENA 21 1 read-write FH1_CBC_INT_ENA 22 1 read-write FH2_CBC_INT_ENA 23 1 read-write FH0_OST_INT_ENA 24 1 read-write FH1_OST_INT_ENA 25 1 read-write FH2_OST_INT_ENA 26 1 read-write CAP0_INT_ENA 27 1 read-write CAP1_INT_ENA 28 1 read-write CAP2_INT_ENA 29 1 read-write INT_RAW 0x114 0x20 TIMER0_STOP_INT_RAW 0 1 read-only TIMER1_STOP_INT_RAW 1 1 read-only TIMER2_STOP_INT_RAW 2 1 read-only TIMER0_TEZ_INT_RAW 3 1 read-only TIMER1_TEZ_INT_RAW 4 1 read-only TIMER2_TEZ_INT_RAW 5 1 read-only TIMER0_TEP_INT_RAW 6 1 read-only TIMER1_TEP_INT_RAW 7 1 read-only TIMER2_TEP_INT_RAW 8 1 read-only FAULT0_INT_RAW 9 1 read-only FAULT1_INT_RAW 10 1 read-only FAULT2_INT_RAW 11 1 read-only FAULT0_CLR_INT_RAW 12 1 read-only FAULT1_CLR_INT_RAW 13 1 read-only FAULT2_CLR_INT_RAW 14 1 read-only OP0_TEA_INT_RAW 15 1 read-only OP1_TEA_INT_RAW 16 1 read-only OP2_TEA_INT_RAW 17 1 read-only OP0_TEB_INT_RAW 18 1 read-only OP1_TEB_INT_RAW 19 1 read-only OP2_TEB_INT_RAW 20 1 read-only FH0_CBC_INT_RAW 21 1 read-only FH1_CBC_INT_RAW 22 1 read-only FH2_CBC_INT_RAW 23 1 read-only FH0_OST_INT_RAW 24 1 read-only FH1_OST_INT_RAW 25 1 read-only FH2_OST_INT_RAW 26 1 read-only CAP0_INT_RAW 27 1 read-only CAP1_INT_RAW 28 1 read-only CAP2_INT_RAW 29 1 read-only INT_ST 0x118 0x20 TIMER0_STOP_INT_ST 0 1 read-only TIMER1_STOP_INT_ST 1 1 read-only TIMER2_STOP_INT_ST 2 1 read-only TIMER0_TEZ_INT_ST 3 1 read-only TIMER1_TEZ_INT_ST 4 1 read-only TIMER2_TEZ_INT_ST 5 1 read-only TIMER0_TEP_INT_ST 6 1 read-only TIMER1_TEP_INT_ST 7 1 read-only TIMER2_TEP_INT_ST 8 1 read-only FAULT0_INT_ST 9 1 read-only FAULT1_INT_ST 10 1 read-only FAULT2_INT_ST 11 1 read-only FAULT0_CLR_INT_ST 12 1 read-only FAULT1_CLR_INT_ST 13 1 read-only FAULT2_CLR_INT_ST 14 1 read-only OP0_TEA_INT_ST 15 1 read-only OP1_TEA_INT_ST 16 1 read-only OP2_TEA_INT_ST 17 1 read-only OP0_TEB_INT_ST 18 1 read-only OP1_TEB_INT_ST 19 1 read-only OP2_TEB_INT_ST 20 1 read-only FH0_CBC_INT_ST 21 1 read-only FH1_CBC_INT_ST 22 1 read-only FH2_CBC_INT_ST 23 1 read-only FH0_OST_INT_ST 24 1 read-only FH1_OST_INT_ST 25 1 read-only FH2_OST_INT_ST 26 1 read-only CAP0_INT_ST 27 1 read-only CAP1_INT_ST 28 1 read-only CAP2_INT_ST 29 1 read-only INT_CLR 0x11C 0x20 TIMER0_STOP_INT_CLR 0 1 write-only TIMER1_STOP_INT_CLR 1 1 write-only TIMER2_STOP_INT_CLR 2 1 write-only TIMER0_TEZ_INT_CLR 3 1 write-only TIMER1_TEZ_INT_CLR 4 1 write-only TIMER2_TEZ_INT_CLR 5 1 write-only TIMER0_TEP_INT_CLR 6 1 write-only TIMER1_TEP_INT_CLR 7 1 write-only TIMER2_TEP_INT_CLR 8 1 write-only FAULT0_INT_CLR 9 1 write-only FAULT1_INT_CLR 10 1 write-only FAULT2_INT_CLR 11 1 write-only FAULT0_CLR_INT_CLR 12 1 write-only FAULT1_CLR_INT_CLR 13 1 write-only FAULT2_CLR_INT_CLR 14 1 write-only OP0_TEA_INT_CLR 15 1 write-only OP1_TEA_INT_CLR 16 1 write-only OP2_TEA_INT_CLR 17 1 write-only OP0_TEB_INT_CLR 18 1 write-only OP1_TEB_INT_CLR 19 1 write-only OP2_TEB_INT_CLR 20 1 write-only FH0_CBC_INT_CLR 21 1 write-only FH1_CBC_INT_CLR 22 1 write-only FH2_CBC_INT_CLR 23 1 write-only FH0_OST_INT_CLR 24 1 write-only FH1_OST_INT_CLR 25 1 write-only FH2_OST_INT_CLR 26 1 write-only CAP0_INT_CLR 27 1 write-only CAP1_INT_CLR 28 1 write-only CAP2_INT_CLR 29 1 write-only CLK 0x120 0x20 EN 0 1 read-write VERSION 0x124 0x20 0x02107230 DATE 0 28 read-write PWM1 Motor Control Pulse-Width Modulation 0x3FF6C000 PWM1 40 NRX Peripheral NRX NRX 0x3FF5CC00 0x0 0x4 registers NRXPD_CTRL WiFi RX control register 0xD4 0x20 DEMAP_FORCE_PD 0 1 read-write DEMAP_FORCE_PU 1 1 read-write VIT_FORCE_PD 2 1 read-write VIT_FORCE_PU 3 1 read-write RX_ROT_FORCE_PD 4 1 read-write RX_ROT_FORCE_PU 5 1 read-write CHAN_EST_FORCE_PD 6 1 read-write CHAN_EST_FORCE_PU 7 1 read-write PCNT Pulse Count Controller PCNT 0x3FF57000 0x0 0xB8 registers PCNT 48 U0_CONF0 0x0 0x20 0x00003C10 FILTER_THRES_U0 This register is used to filter pluse whose width is smaller than this value for unit0. 0 10 read-write FILTER_EN_U0 This is the enable bit for filtering input signals for unit0. 10 1 read-write THR_ZERO_EN_U0 This is the enable bit for comparing unit0's count with 0 value. 11 1 read-write THR_H_LIM_EN_U0 This is the enable bit for comparing unit0's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U0 This is the enable bit for comparing unit0's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U0 This is the enable bit for comparing unit0's count with thres0 value. 14 1 read-write THR_THRES1_EN_U0 This is the enable bit for comparing unit0's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U0 This register is used to control the mode of channel0's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U0 This register is used to control the mode of channel0's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U0 This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U0 This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U0 This register is used to control the mode of channel1's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U0 This register is used to control the mode of channel1's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U0 This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U0 This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U0_CONF1 0x4 0x20 CNT_THRES0_U0 This register is used to configure thres0 value for unit0. 0 16 read-write CNT_THRES1_U0 This register is used to configure thres1 value for unit0. 16 16 read-write U0_CONF2 0x8 0x20 CNT_H_LIM_U0 This register is used to configure thr_h_lim value for unit0. 0 16 read-write CNT_L_LIM_U0 This register is used to confiugre thr_l_lim value for unit0. 16 16 read-write U1_CONF0 0xC 0x20 0x00003C10 FILTER_THRES_U1 This register is used to filter pluse whose width is smaller than this value for unit1. 0 10 read-write FILTER_EN_U1 This is the enable bit for filtering input signals for unit1. 10 1 read-write THR_ZERO_EN_U1 This is the enable bit for comparing unit1's count with 0 value. 11 1 read-write THR_H_LIM_EN_U1 This is the enable bit for comparing unit1's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U1 This is the enable bit for comparing unit1's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U1 This is the enable bit for comparing unit1's count with thres0 value. 14 1 read-write THR_THRES1_EN_U1 This is the enable bit for comparing unit1's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U1 This register is used to control the mode of channel0's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U1 This register is used to control the mode of channel0's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U1 This register is used to control the mode of channel0's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U1 This register is used to control the mode of channel0's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U1 This register is used to control the mode of channel1's input negedge signal for unit1. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U1 This register is used to control the mode of channel1's input posedge signal for unit1. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U1 This register is used to control the mode of channel1's high control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U1 This register is used to control the mode of channel1's low control signal for unit1. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U1_CONF1 0x10 0x20 CNT_THRES0_U1 This register is used to configure thres0 value for unit1. 0 16 read-write CNT_THRES1_U1 This register is used to configure thres1 value for unit1. 16 16 read-write U1_CONF2 0x14 0x20 CNT_H_LIM_U1 This register is used to configure thr_h_lim value for unit1. 0 16 read-write CNT_L_LIM_U1 This register is used to confiugre thr_l_lim value for unit1. 16 16 read-write U2_CONF0 0x18 0x20 0x00003C10 FILTER_THRES_U2 This register is used to filter pluse whose width is smaller than this value for unit2. 0 10 read-write FILTER_EN_U2 This is the enable bit for filtering input signals for unit2. 10 1 read-write THR_ZERO_EN_U2 This is the enable bit for comparing unit2's count with 0 value. 11 1 read-write THR_H_LIM_EN_U2 This is the enable bit for comparing unit2's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U2 This is the enable bit for comparing unit2's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U2 This is the enable bit for comparing unit2's count with thres0 value. 14 1 read-write THR_THRES1_EN_U2 This is the enable bit for comparing unit2's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U2 This register is used to control the mode of channel0's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U2 This register is used to control the mode of channel0's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U2 This register is used to control the mode of channel0's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U2 This register is used to control the mode of channel0's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U2 This register is used to control the mode of channel1's input negedge signal for unit2. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U2 This register is used to control the mode of channel1's input posedge signal for unit2. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U2 This register is used to control the mode of channel1's high control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U2 This register is used to control the mode of channel1's low control signal for unit2. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U2_CONF1 0x1C 0x20 CNT_THRES0_U2 This register is used to configure thres0 value for unit2. 0 16 read-write CNT_THRES1_U2 This register is used to configure thres1 value for unit2. 16 16 read-write U2_CONF2 0x20 0x20 CNT_H_LIM_U2 This register is used to configure thr_h_lim value for unit2. 0 16 read-write CNT_L_LIM_U2 This register is used to confiugre thr_l_lim value for unit2. 16 16 read-write U3_CONF0 0x24 0x20 0x00003C10 FILTER_THRES_U3 This register is used to filter pluse whose width is smaller than this value for unit3. 0 10 read-write FILTER_EN_U3 This is the enable bit for filtering input signals for unit3. 10 1 read-write THR_ZERO_EN_U3 This is the enable bit for comparing unit3's count with 0 value. 11 1 read-write THR_H_LIM_EN_U3 This is the enable bit for comparing unit3's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U3 This is the enable bit for comparing unit3's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U3 This is the enable bit for comparing unit3's count with thres0 value. 14 1 read-write THR_THRES1_EN_U3 This is the enable bit for comparing unit3's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U3 This register is used to control the mode of channel0's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U3 This register is used to control the mode of channel0's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U3 This register is used to control the mode of channel0's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U3 This register is used to control the mode of channel0's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U3 This register is used to control the mode of channel1's input negedge signal for unit3. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U3 This register is used to control the mode of channel1's input posedge signal for unit3. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U3 This register is used to control the mode of channel1's high control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U3 This register is used to control the mode of channel1's low control signal for unit3. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U3_CONF1 0x28 0x20 CNT_THRES0_U3 This register is used to configure thres0 value for unit3. 0 16 read-write CNT_THRES1_U3 This register is used to configure thres1 value for unit3. 16 16 read-write U3_CONF2 0x2C 0x20 CNT_H_LIM_U3 This register is used to configure thr_h_lim value for unit3. 0 16 read-write CNT_L_LIM_U3 This register is used to confiugre thr_l_lim value for unit3. 16 16 read-write U4_CONF0 0x30 0x20 0x00003C10 FILTER_THRES_U4 This register is used to filter pluse whose width is smaller than this value for unit4. 0 10 read-write FILTER_EN_U4 This is the enable bit for filtering input signals for unit4. 10 1 read-write THR_ZERO_EN_U4 This is the enable bit for comparing unit4's count with 0 value. 11 1 read-write THR_H_LIM_EN_U4 This is the enable bit for comparing unit4's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U4 This is the enable bit for comparing unit4's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U4 This is the enable bit for comparing unit4's count with thres0 value. 14 1 read-write THR_THRES1_EN_U4 This is the enable bit for comparing unit4's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U4 This register is used to control the mode of channel0's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U4 This register is used to control the mode of channel0's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U4 This register is used to control the mode of channel0's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U4 This register is used to control the mode of channel0's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U4 This register is used to control the mode of channel1's input negedge signal for unit4. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U4 This register is used to control the mode of channel1's input posedge signal for unit4. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U4 This register is used to control the mode of channel1's high control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U4 This register is used to control the mode of channel1's low control signal for unit4. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U4_CONF1 0x34 0x20 CNT_THRES0_U4 This register is used to configure thres0 value for unit4. 0 16 read-write CNT_THRES1_U4 This register is used to configure thres1 value for unit4. 16 16 read-write U4_CONF2 0x38 0x20 CNT_H_LIM_U4 This register is used to configure thr_h_lim value for unit4. 0 16 read-write CNT_L_LIM_U4 This register is used to confiugre thr_l_lim value for unit4. 16 16 read-write U5_CONF0 0x3C 0x20 0x00003C10 FILTER_THRES_U5 This register is used to filter pluse whose width is smaller than this value for unit5. 0 10 read-write FILTER_EN_U5 This is the enable bit for filtering input signals for unit5. 10 1 read-write THR_ZERO_EN_U5 This is the enable bit for comparing unit5's count with 0 value. 11 1 read-write THR_H_LIM_EN_U5 This is the enable bit for comparing unit5's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U5 This is the enable bit for comparing unit5's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U5 This is the enable bit for comparing unit5's count with thres0 value. 14 1 read-write THR_THRES1_EN_U5 This is the enable bit for comparing unit5's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U5 This register is used to control the mode of channel0's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U5 This register is used to control the mode of channel0's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U5 This register is used to control the mode of channel0's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U5 This register is used to control the mode of channel0's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U5 This register is used to control the mode of channel1's input negedge signal for unit5. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U5 This register is used to control the mode of channel1's input posedge signal for unit5. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U5 This register is used to control the mode of channel1's high control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U5 This register is used to control the mode of channel1's low control signal for unit5. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U5_CONF1 0x40 0x20 CNT_THRES0_U5 This register is used to configure thres0 value for unit5. 0 16 read-write CNT_THRES1_U5 This register is used to configure thres1 value for unit5. 16 16 read-write U5_CONF2 0x44 0x20 CNT_H_LIM_U5 This register is used to configure thr_h_lim value for unit5. 0 16 read-write CNT_L_LIM_U5 This register is used to confiugre thr_l_lim value for unit5. 16 16 read-write U6_CONF0 0x48 0x20 0x00003C10 FILTER_THRES_U6 This register is used to filter pluse whose width is smaller than this value for unit6. 0 10 read-write FILTER_EN_U6 This is the enable bit for filtering input signals for unit6. 10 1 read-write THR_ZERO_EN_U6 This is the enable bit for comparing unit6's count with 0 value. 11 1 read-write THR_H_LIM_EN_U6 This is the enable bit for comparing unit6's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U6 This is the enable bit for comparing unit6's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U6 This is the enable bit for comparing unit6's count with thres0 value. 14 1 read-write THR_THRES1_EN_U6 This is the enable bit for comparing unit6's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U6 This register is used to control the mode of channel0's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U6 This register is used to control the mode of channel0's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U6 This register is used to control the mode of channel0's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U6 This register is used to control the mode of channel0's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U6 This register is used to control the mode of channel1's input negedge signal for unit6. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U6 This register is used to control the mode of channel1's input posedge signal for unit6. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U6 This register is used to control the mode of channel1's high control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U6 This register is used to control the mode of channel1's low control signal for unit6. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U6_CONF1 0x4C 0x20 CNT_THRES0_U6 This register is used to configure thres0 value for unit6. 0 16 read-write CNT_THRES1_U6 This register is used to configure thres1 value for unit6. 16 16 read-write U6_CONF2 0x50 0x20 CNT_H_LIM_U6 This register is used to configure thr_h_lim value for unit6. 0 16 read-write CNT_L_LIM_U6 This register is used to confiugre thr_l_lim value for unit6. 16 16 read-write U7_CONF0 0x54 0x20 0x00003C10 FILTER_THRES_U7 This register is used to filter pluse whose width is smaller than this value for unit7. 0 10 read-write FILTER_EN_U7 This is the enable bit for filtering input signals for unit7. 10 1 read-write THR_ZERO_EN_U7 This is the enable bit for comparing unit7's count with 0 value. 11 1 read-write THR_H_LIM_EN_U7 This is the enable bit for comparing unit7's count with thr_h_lim value. 12 1 read-write THR_L_LIM_EN_U7 This is the enable bit for comparing unit7's count with thr_l_lim value. 13 1 read-write THR_THRES0_EN_U7 This is the enable bit for comparing unit7's count with thres0 value. 14 1 read-write THR_THRES1_EN_U7 This is the enable bit for comparing unit7's count with thres1 value . 15 1 read-write CH0_NEG_MODE_U7 This register is used to control the mode of channel0's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 16 2 read-write CH0_POS_MODE_U7 This register is used to control the mode of channel0's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 18 2 read-write CH0_HCTRL_MODE_U7 This register is used to control the mode of channel0's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 20 2 read-write CH0_LCTRL_MODE_U7 This register is used to control the mode of channel0's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 22 2 read-write CH1_NEG_MODE_U7 This register is used to control the mode of channel1's input negedge signal for unit7. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden 24 2 read-write CH1_POS_MODE_U7 This register is used to control the mode of channel1's input posedge signal for unit7. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden 26 2 read-write CH1_HCTRL_MODE_U7 This register is used to control the mode of channel1's high control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 28 2 read-write CH1_LCTRL_MODE_U7 This register is used to control the mode of channel1's low control signal for unit7. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden 30 2 read-write U7_CONF1 0x58 0x20 CNT_THRES0_U7 This register is used to configure thres0 value for unit7. 0 16 read-write CNT_THRES1_U7 This register is used to configure thres1 value for unit7. 16 16 read-write U7_CONF2 0x5C 0x20 CNT_H_LIM_U7 This register is used to configure thr_h_lim value for unit7. 0 16 read-write CNT_L_LIM_U7 This register is used to confiugre thr_l_lim value for unit7. 16 16 read-write U0_CNT 0x60 0x20 PLUS_CNT_U0 This register stores the current pulse count value for unit0. 0 16 read-only U1_CNT 0x64 0x20 PLUS_CNT_U1 This register stores the current pulse count value for unit1. 0 16 read-only U2_CNT 0x68 0x20 PLUS_CNT_U2 This register stores the current pulse count value for unit2. 0 16 read-only U3_CNT 0x6C 0x20 PLUS_CNT_U3 This register stores the current pulse count value for unit3. 0 16 read-only U4_CNT 0x70 0x20 PLUS_CNT_U4 This register stores the current pulse count value for unit4. 0 16 read-only U5_CNT 0x74 0x20 PLUS_CNT_U5 This register stores the current pulse count value for unit5. 0 16 read-only U6_CNT 0x78 0x20 PLUS_CNT_U6 This register stores the current pulse count value for unit6. 0 16 read-only U7_CNT 0x7C 0x20 PLUS_CNT_U7 This register stores the current pulse count value for unit7. 0 16 read-only INT_RAW 0x80 0x20 CNT_THR_EVENT_U0_INT_RAW This is the interrupt raw bit for channel0 event. 0 1 read-only CNT_THR_EVENT_U1_INT_RAW This is the interrupt raw bit for channel1 event. 1 1 read-only CNT_THR_EVENT_U2_INT_RAW This is the interrupt raw bit for channel2 event. 2 1 read-only CNT_THR_EVENT_U3_INT_RAW This is the interrupt raw bit for channel3 event. 3 1 read-only CNT_THR_EVENT_U4_INT_RAW This is the interrupt raw bit for channel4 event. 4 1 read-only CNT_THR_EVENT_U5_INT_RAW This is the interrupt raw bit for channel5 event. 5 1 read-only CNT_THR_EVENT_U6_INT_RAW This is the interrupt raw bit for channel6 event. 6 1 read-only CNT_THR_EVENT_U7_INT_RAW This is the interrupt raw bit for channel7 event. 7 1 read-only INT_ST 0x84 0x20 CNT_THR_EVENT_U0_INT_ST This is the interrupt status bit for channel0 event. 0 1 read-only CNT_THR_EVENT_U1_INT_ST This is the interrupt status bit for channel1 event. 1 1 read-only CNT_THR_EVENT_U2_INT_ST This is the interrupt status bit for channel2 event. 2 1 read-only CNT_THR_EVENT_U3_INT_ST This is the interrupt status bit for channel3 event. 3 1 read-only CNT_THR_EVENT_U4_INT_ST This is the interrupt status bit for channel4 event. 4 1 read-only CNT_THR_EVENT_U5_INT_ST This is the interrupt status bit for channel5 event. 5 1 read-only CNT_THR_EVENT_U6_INT_ST This is the interrupt status bit for channel6 event. 6 1 read-only CNT_THR_EVENT_U7_INT_ST This is the interrupt status bit for channel7 event. 7 1 read-only INT_ENA 0x88 0x20 CNT_THR_EVENT_U0_INT_ENA This is the interrupt enable bit for channel0 event. 0 1 read-write CNT_THR_EVENT_U1_INT_ENA This is the interrupt enable bit for channel1 event. 1 1 read-write CNT_THR_EVENT_U2_INT_ENA This is the interrupt enable bit for channel2 event. 2 1 read-write CNT_THR_EVENT_U3_INT_ENA This is the interrupt enable bit for channel3 event. 3 1 read-write CNT_THR_EVENT_U4_INT_ENA This is the interrupt enable bit for channel4 event. 4 1 read-write CNT_THR_EVENT_U5_INT_ENA This is the interrupt enable bit for channel5 event. 5 1 read-write CNT_THR_EVENT_U6_INT_ENA This is the interrupt enable bit for channel6 event. 6 1 read-write CNT_THR_EVENT_U7_INT_ENA This is the interrupt enable bit for channel7 event. 7 1 read-write INT_CLR 0x8C 0x20 CNT_THR_EVENT_U0_INT_CLR Set this bit to clear channel0 event interrupt. 0 1 write-only CNT_THR_EVENT_U1_INT_CLR Set this bit to clear channel1 event interrupt. 1 1 write-only CNT_THR_EVENT_U2_INT_CLR Set this bit to clear channel2 event interrupt. 2 1 write-only CNT_THR_EVENT_U3_INT_CLR Set this bit to clear channel3 event interrupt. 3 1 write-only CNT_THR_EVENT_U4_INT_CLR Set this bit to clear channel4 event interrupt. 4 1 write-only CNT_THR_EVENT_U5_INT_CLR Set this bit to clear channel5 event interrupt. 5 1 write-only CNT_THR_EVENT_U6_INT_CLR Set this bit to clear channel6 event interrupt. 6 1 write-only CNT_THR_EVENT_U7_INT_CLR Set this bit to clear channel7 event interrupt. 7 1 write-only U0_STATUS 0x90 0x20 CORE_STATUS_U0 0 32 read-only STATUS_CNT_MODE 0 2 read-write STATUS_THRES1 2 1 read-write STATUS_THRES0 3 1 read-write STATUS_L_LIM 4 1 read-write STATUS_H_LIM 5 1 read-write STATUS_ZERO 6 1 read-write U1_STATUS 0x94 0x20 CORE_STATUS_U1 0 32 read-only U2_STATUS 0x98 0x20 CORE_STATUS_U2 0 32 read-only U3_STATUS 0x9C 0x20 CORE_STATUS_U3 0 32 read-only U4_STATUS 0xA0 0x20 CORE_STATUS_U4 0 32 read-only U5_STATUS 0xA4 0x20 CORE_STATUS_U5 0 32 read-only U6_STATUS 0xA8 0x20 CORE_STATUS_U6 0 32 read-only U7_STATUS 0xAC 0x20 CORE_STATUS_U7 0 32 read-only CTRL 0xB0 0x20 0x00005555 PLUS_CNT_RST_U0 Set this bit to clear unit0's counter. 0 1 read-write CNT_PAUSE_U0 Set this bit to pause unit0's counter. 1 1 read-write PLUS_CNT_RST_U1 Set this bit to clear unit1's counter. 2 1 read-write CNT_PAUSE_U1 Set this bit to pause unit1's counter. 3 1 read-write PLUS_CNT_RST_U2 Set this bit to clear unit2's counter. 4 1 read-write CNT_PAUSE_U2 Set this bit to pause unit2's counter. 5 1 read-write PLUS_CNT_RST_U3 Set this bit to clear unit3's counter. 6 1 read-write CNT_PAUSE_U3 Set this bit to pause unit3's counter. 7 1 read-write PLUS_CNT_RST_U4 Set this bit to clear unit4's counter. 8 1 read-write CNT_PAUSE_U4 Set this bit to pause unit4's counter. 9 1 read-write PLUS_CNT_RST_U5 Set this bit to clear unit5's counter. 10 1 read-write CNT_PAUSE_U5 Set this bit to pause unit5's counter. 11 1 read-write PLUS_CNT_RST_U6 Set this bit to clear unit6's counter. 12 1 read-write CNT_PAUSE_U6 Set this bit to pause unit6's counter. 13 1 read-write PLUS_CNT_RST_U7 Set this bit to clear unit7's counter. 14 1 read-write CNT_PAUSE_U7 Set this bit to pause unit7's counter. 15 1 read-write CLK_EN 16 1 read-write DATE 0xFC 0x20 0x14122600 DATE 0 32 read-write RMT Remote Control Peripheral RMT 0x3FF56000 0x0 0xF8 registers RMT 47 CH0DATA 0x0 0x20 CH1DATA 0x4 0x20 CH2DATA 0x8 0x20 CH3DATA 0xC 0x20 CH4DATA 0x10 0x20 CH5DATA 0x14 0x20 CH6DATA 0x18 0x20 CH7DATA 0x1C 0x20 8 0x8 0-7 CH%sCONF0 0x20 0x20 0x31100002 DIV_CNT This register is used to configure the frequency divider's factor in channel0. 0 8 read-write IDLE_THRES In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done. 8 16 read-write MEM_SIZE This register is used to configure the the amount of memory blocks allocated to channel0. 24 4 read-write CARRIER_EN This is the carrier modulation enable control bit for channel0. 28 1 read-write CARRIER_OUT_LV This bit is used to configure the way carrier wave is modulated for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level. 29 1 read-write MEM_PD This bit is used to reduce power consumed by mem. 1:mem is in low power state. 30 1 read-write CLK_EN This bit is used to control clock.when software config RMT internal registers it controls the register clock. 31 1 read-write 8 0x8 0-7 CH%sCONF1 0x24 0x20 0x00000F20 TX_START Set this bit to start sending data for channel0. 0 1 read-write RX_EN Set this bit to enbale receving data for channel0. 1 1 read-write MEM_WR_RST Set this bit to reset write ram address for channel0 by receiver access. 2 1 read-write MEM_RD_RST Set this bit to reset read ram address for channel0 by transmitter access. 3 1 read-write APB_MEM_RST Set this bit to reset W/R ram address for channel0 by apb fifo access 4 1 read-write MEM_OWNER This is the mark of channel0's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram 5 1 read-write TX_CONTI_MODE Set this bit to continue sending from the first data to the last data in channel0 again and again. 6 1 read-write RX_FILTER_EN This is the receive filter enable bit for channel0. 7 1 read-write RX_FILTER_THRES in receive mode channel0 ignore input pulse when the pulse width is smaller then this value. 8 8 read-write REF_CNT_RST This bit is used to reset divider in channel0. 16 1 read-write REF_ALWAYS_ON This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref 17 1 read-write IDLE_OUT_LV This bit configures the output signal's level for channel0 in IDLE state. 18 1 read-write IDLE_OUT_EN This is the output enable control bit for channel0 in IDLE state. 19 1 read-write CH0STATUS 0x60 0x20 STATUS The status for channel0 0 32 read-only MEM_WADDR_EX The current memory read address of channel0. 0 10 read-only MEM_RADDR_EX The current memory write address of channel0. 12 10 read-only STATE The channel0 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH1STATUS 0x64 0x20 STATUS The status for channel1 0 32 read-only MEM_WADDR_EX The current memory read address of channel1. 0 10 read-only MEM_RADDR_EX The current memory write address of channel1. 12 10 read-only STATE The channel1 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel1 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel1 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel1. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel1 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel1 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH2STATUS 0x68 0x20 STATUS The status for channel2 0 32 read-only MEM_WADDR_EX The current memory read address of channel2. 0 10 read-only MEM_RADDR_EX The current memory write address of channel2. 12 10 read-only STATE The channel2 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel2 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel2 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel2. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel2 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel2 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH3STATUS 0x6C 0x20 STATUS The status for channel3 0 32 read-only MEM_WADDR_EX The current memory read address of channel3. 0 10 read-only MEM_RADDR_EX The current memory write address of channel3. 12 10 read-only STATE The channel3 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel3 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel3 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel3. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel3 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel3 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH4STATUS 0x70 0x20 STATUS The status for channel4 0 32 read-only MEM_WADDR_EX The current memory read address of channel4. 0 10 read-only MEM_RADDR_EX The current memory write address of channel4. 12 10 read-only STATE The channel4 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel4 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel4 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel4. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel4 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel4 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH5STATUS 0x74 0x20 STATUS The status for channel5 0 32 read-only MEM_WADDR_EX The current memory read address of channel5. 0 10 read-only MEM_RADDR_EX The current memory write address of channel5. 12 10 read-only STATE The channel5 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel5 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel5 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel5. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel5 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel5 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH6STATUS 0x78 0x20 STATUS The status for channel6 0 32 read-only MEM_WADDR_EX The current memory read address of channel6. 0 10 read-only MEM_RADDR_EX The current memory write address of channel6. 12 10 read-only STATE The channel6 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel6 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel6 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel6. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel6 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel6 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH7STATUS 0x7C 0x20 STATUS The status for channel7 0 32 read-only MEM_WADDR_EX The current memory read address of channel7. 0 10 read-only MEM_RADDR_EX The current memory write address of channel7. 12 10 read-only STATE The channel7 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait. 24 3 read-only MEM_OWNER_ERR When channel7 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1. 27 1 read-only MEM_FULL The memory full status bit for channel7 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. 28 1 read-only MEM_EMPTY The memory empty status bit for channel7. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range. 29 1 read-only APB_MEM_WR_ERR The apb write memory status bit for channel7 turns to high level when the apb write address exceeds the configuration range. 30 1 read-only APB_MEM_RD_ERR The apb read memory status bit for channel7 turns to high level when the apb read address exceeds the configuration range. 31 1 read-only CH0ADDR 0x80 0x20 APB_MEM_ADDR The ram relative address in channel0 by apb fifo access 0 32 read-only CH1ADDR 0x84 0x20 APB_MEM_ADDR The ram relative address in channel1 by apb fifo access 0 32 read-only CH2ADDR 0x88 0x20 APB_MEM_ADDR The ram relative address in channel2 by apb fifo access 0 32 read-only CH3ADDR 0x8C 0x20 APB_MEM_ADDR The ram relative address in channel3 by apb fifo access 0 32 read-only CH4ADDR 0x90 0x20 APB_MEM_ADDR The ram relative address in channel4 by apb fifo access 0 32 read-only CH5ADDR 0x94 0x20 APB_MEM_ADDR The ram relative address in channel5 by apb fifo access 0 32 read-only CH6ADDR 0x98 0x20 APB_MEM_ADDR The ram relative address in channel6 by apb fifo access 0 32 read-only CH7ADDR 0x9C 0x20 APB_MEM_ADDR The ram relative address in channel7 by apb fifo access 0 32 read-only INT_RAW 0xA0 0x20 8 0x3 0-7 CH%s_TX_END_INT_RAW The interrupt raw bit for channel %s turns to high level when the transmit process is done. 0 1 read-only 8 0x3 0-7 CH%s_RX_END_INT_RAW The interrupt raw bit for channel %s turns to high level when the receive process is done. 1 1 read-only 8 0x3 0-7 CH%s_ERR_INT_RAW The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. 2 1 read-only 8 0x1 0-7 CH%s_TX_THR_EVENT_INT_RAW The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. 24 1 read-only INT_ST 0xA4 0x20 8 0x3 0-7 CH%s_TX_END_INT_ST The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s. 0 1 read-only 8 0x3 0-7 CH%s_RX_END_INT_ST The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s. 1 1 read-only 8 0x3 0-7 CH%s_ERR_INT_ST The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s. 2 1 read-only 8 0x1 0-7 CH%s_TX_THR_EVENT_INT_ST The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1. 24 1 read-only INT_ENA 0xA8 0x20 8 0x3 0-7 CH%s_TX_END_INT_ENA Set this bit to enable rmt_ch%s_tx_end_int_st. 0 1 read-write 8 0x3 0-7 CH%s_RX_END_INT_ENA Set this bit to enable rmt_ch%s_rx_end_int_st. 1 1 read-write 8 0x3 0-7 CH%s_ERR_INT_ENA Set this bit to enable rmt_ch%s_err_int_st. 2 1 read-write 8 0x1 0-7 CH%s_TX_THR_EVENT_INT_ENA Set this bit to enable rmt_ch%s_tx_thr_event_int_st. 24 1 read-write INT_CLR 0xAC 0x20 8 0x3 0-7 CH%s_TX_END_INT_CLR Set this bit to clear the rmt_ch%s_rx_end_int_raw.. 0 1 write-only 8 0x3 0-7 CH%s_RX_END_INT_CLR Set this bit to clear the rmt_ch%s_tx_end_int_raw. 1 1 write-only 8 0x3 0-7 CH%s_ERR_INT_CLR Set this bit to clear the rmt_ch%s_err_int_raw. 2 1 write-only 8 0x1 0-7 CH%s_TX_THR_EVENT_INT_CLR Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. 24 1 write-only CH0CARRIER_DUTY 0xB0 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel0. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel0. 16 16 read-write CH1CARRIER_DUTY 0xB4 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel1. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel1. 16 16 read-write CH2CARRIER_DUTY 0xB8 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel2. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel2. 16 16 read-write CH3CARRIER_DUTY 0xBC 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel3. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel3. 16 16 read-write CH4CARRIER_DUTY 0xC0 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel4. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel4. 16 16 read-write CH5CARRIER_DUTY 0xC4 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel5. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel5. 16 16 read-write CH6CARRIER_DUTY 0xC8 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel6. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel6. 16 16 read-write CH7CARRIER_DUTY 0xCC 0x20 0x00400040 CARRIER_LOW This register is used to configure carrier wave's low level value for channel7. 0 16 read-write CARRIER_HIGH This register is used to configure carrier wave's high level value for channel7. 16 16 read-write 8 0x4 0-7 CH%s_TX_LIM 0xD0 0x20 0x00000080 TX_LIM When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 produce the relative interrupt. 0 9 read-write APB_CONF 0xF0 0x20 APB_FIFO_MASK Set this bit to disable apb fifo access 0 1 read-write MEM_TX_WRAP_EN when datas need to be send is more than channel's mem can store then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn. 1 1 read-write DATE 0xFC 0x20 0x16022600 DATE This is the version register. 0 32 read-write RNG Hardware random number generator RNG 0x60035000 0x0 0x4 registers DATA Random number data 0x144 0x20 RSA RSA (Rivest Shamir Adleman) Accelerator RSA 0x3FF02000 0x0 0x1C registers RSA 51 M_PRIME 0x0 0x20 M_PRIME This register contains M’. 0 8 read-write MODEXP_MODE 0x4 0x20 MODEXP_MODE This register contains the mode of modular exponentiation. 0 2 read-write MODEXP_START 0x8 0x20 MODEXP_START Write 1 to start modular exponentiation. 0 1 write-only MULT_MODE 0xC 0x20 MULT_MODE This register contains the mode of modular multiplication and multiplication. 0 1 read-write MULT_START 0x10 0x20 MULT_START Write 1 to start modular multiplication or multiplication. 0 1 write-only INTERRUPT 0x14 0x20 INTERRUPT RSA interrupt status register. Will read 1 once an operation has completed. 0 1 read-write CLEAN 0x18 0x20 CLEAN This bit will read 1 once the memory initialization is completed. 0 1 read-only RTC_CNTL Real-Time Clock Control RTC_CNTL 0x3FF48000 0x0 0xDC registers RTC_CORE 46 OPTIONS0 0x0 0x20 0x1C492000 SW_STALL_APPCPU_C0 {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU 0 2 read-write SW_STALL_PROCPU_C0 {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU 2 2 read-write SW_APPCPU_RST APP CPU SW reset 4 1 write-only SW_PROCPU_RST PRO CPU SW reset 5 1 write-only BB_I2C_FORCE_PD BB_I2C force power down 6 1 read-write BB_I2C_FORCE_PU BB_I2C force power up 7 1 read-write BBPLL_I2C_FORCE_PD BB_PLL _I2C force power down 8 1 read-write BBPLL_I2C_FORCE_PU BB_PLL_I2C force power up 9 1 read-write BBPLL_FORCE_PD BB_PLL force power down 10 1 read-write BBPLL_FORCE_PU BB_PLL force power up 11 1 read-write XTL_FORCE_PD crystall force power down 12 1 read-write XTL_FORCE_PU crystall force power up 13 1 read-write BIAS_SLEEP_FOLW_8M BIAS_SLEEP follow CK8M 14 1 read-write BIAS_FORCE_SLEEP BIAS_SLEEP force sleep 15 1 read-write BIAS_FORCE_NOSLEEP BIAS_SLEEP force no sleep 16 1 read-write BIAS_I2C_FOLW_8M BIAS_I2C follow CK8M 17 1 read-write BIAS_I2C_FORCE_PD BIAS_I2C force power down 18 1 read-write BIAS_I2C_FORCE_PU BIAS_I2C force power up 19 1 read-write BIAS_CORE_FOLW_8M BIAS_CORE follow CK8M 20 1 read-write BIAS_CORE_FORCE_PD BIAS_CORE force power down 21 1 read-write BIAS_CORE_FORCE_PU BIAS_CORE force power up 22 1 read-write XTL_FORCE_ISO 23 1 read-write PLL_FORCE_ISO 24 1 read-write ANALOG_FORCE_ISO 25 1 read-write XTL_FORCE_NOISO 26 1 read-write PLL_FORCE_NOISO 27 1 read-write ANALOG_FORCE_NOISO 28 1 read-write DG_WRAP_FORCE_RST digital wrap force reset in deep sleep 29 1 read-write DG_WRAP_FORCE_NORST digital core force no reset in deep sleep 30 1 read-write SW_SYS_RST SW system reset 31 1 write-only SLP_TIMER0 0x4 0x20 SLP_VAL_LO RTC sleep timer low 32 bits 0 32 read-write SLP_TIMER1 0x8 0x20 SLP_VAL_HI RTC sleep timer high 16 bits 0 16 read-write MAIN_TIMER_ALARM_EN timer alarm enable bit 16 1 read-write TIME_UPDATE 0xC 0x20 TIME_VALID To indicate the register is updated 30 1 read-only TIME_UPDATE Set 1: to update register with RTC timer 31 1 write-only TIME0 0x10 0x20 TIME_LO RTC timer low 32 bits 0 32 read-only TIME1 0x14 0x20 TIME_HI RTC timer high 16 bits 0 16 read-only STATE0 0x18 0x20 0x00300000 TOUCH_WAKEUP_FORCE_EN touch controller force wake up 20 1 read-write ULP_CP_WAKEUP_FORCE_EN ULP-coprocessor force wake up 21 1 read-write APB2RTC_BRIDGE_SEL 1: APB to RTC using bridge 0: APB to RTC using sync 22 1 read-write TOUCH_SLP_TIMER_EN touch timer enable bit 23 1 read-write ULP_CP_SLP_TIMER_EN ULP-coprocessor timer enable bit 24 1 read-write SDIO_ACTIVE_IND SDIO active indication 28 1 read-only SLP_WAKEUP sleep wakeup bit 29 1 read-write SLP_REJECT sleep reject bit 30 1 read-write SLEEP_EN sleep enable bit 31 1 read-write TIMER1 0x1C 0x20 0x28140403 CPU_STALL_EN CPU stall enable bit 0 1 read-write CPU_STALL_WAIT CPU stall wait cycles in fast_clk_rtc 1 5 read-write CK8M_WAIT CK8M wait cycles in slow_clk_rtc 6 8 read-write XTL_BUF_WAIT XTAL wait cycles in slow_clk_rtc 14 10 read-write PLL_BUF_WAIT PLL wait cycles in slow_clk_rtc 24 8 read-write TIMER2 0x20 0x20 0x01080000 ULPCP_TOUCH_START_WAIT wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work 15 9 read-write MIN_TIME_CK8M_OFF minimal cycles in slow_clk_rtc for CK8M in power down state 24 8 read-write TIMER3 0x24 0x20 0x14160A08 WIFI_WAIT_TIMER 0 9 read-write WIFI_POWERUP_TIMER 9 7 read-write ROM_RAM_WAIT_TIMER 16 9 read-write ROM_RAM_POWERUP_TIMER 25 7 read-write TIMER4 0x28 0x20 0x10200A08 WAIT_TIMER 0 9 read-write POWERUP_TIMER 9 7 read-write DG_WRAP_WAIT_TIMER 16 9 read-write DG_WRAP_POWERUP_TIMER 25 7 read-write TIMER5 0x2C 0x20 0x12148001 ULP_CP_SUBTIMER_PREDIV 0 8 read-write MIN_SLP_VAL minimal sleep cycles in slow_clk_rtc 8 8 read-write RTCMEM_WAIT_TIMER 16 9 read-write RTCMEM_POWERUP_TIMER 25 7 read-write ANA_CONF 0x30 0x20 0x00800000 PLLA_FORCE_PD PLLA force power down 23 1 read-write PLLA_FORCE_PU PLLA force power up 24 1 read-write BBPLL_CAL_SLP_START start BBPLL calibration during sleep 25 1 read-write PVTMON_PU 1: PVTMON power up otherwise power down 26 1 read-write TXRF_I2C_PU 1: TXRF_I2C power up otherwise power down 27 1 read-write RFRX_PBUS_PU 1: RFRX_PBUS power up otherwise power down 28 1 read-write CKGEN_I2C_PU 1: CKGEN_I2C power up otherwise power down 30 1 read-write PLL_I2C_PU 1: PLL_I2C power up otherwise power down 31 1 read-write RESET_STATE 0x34 0x20 0x00003000 RESET_CAUSE_PROCPU reset cause of PRO CPU 0 6 read-only RESET_CAUSE_APPCPU reset cause of APP CPU 6 6 read-only APPCPU_STAT_VECTOR_SEL APP CPU state vector sel 12 1 read-write PROCPU_STAT_VECTOR_SEL PRO CPU state vector sel 13 1 read-write WAKEUP_STATE 0x38 0x20 0x00006000 WAKEUP_CAUSE wakeup cause 0 11 read-only WAKEUP_ENA wakeup enable bitmap 11 11 read-write GPIO_WAKEUP_FILTER enable filter for gpio wakeup event 22 1 read-write INT_ENA 0x3C 0x20 SLP_WAKEUP_INT_ENA enable sleep wakeup interrupt 0 1 read-write SLP_REJECT_INT_ENA enable sleep reject interrupt 1 1 read-write SDIO_IDLE_INT_ENA enable SDIO idle interrupt 2 1 read-write WDT_INT_ENA enable RTC WDT interrupt 3 1 read-write TIME_VALID_INT_ENA enable RTC time valid interrupt 4 1 read-write ULP_CP_INT_ENA enable ULP-coprocessor interrupt 5 1 read-write TOUCH_INT_ENA enable touch interrupt 6 1 read-write BROWN_OUT_INT_ENA enable brown out interrupt 7 1 read-write MAIN_TIMER_INT_ENA enable RTC main timer interrupt 8 1 read-write INT_RAW 0x40 0x20 SLP_WAKEUP_INT_RAW sleep wakeup interrupt raw 0 1 read-only SLP_REJECT_INT_RAW sleep reject interrupt raw 1 1 read-only SDIO_IDLE_INT_RAW SDIO idle interrupt raw 2 1 read-only WDT_INT_RAW RTC WDT interrupt raw 3 1 read-only TIME_VALID_INT_RAW RTC time valid interrupt raw 4 1 read-only ULP_CP_INT_RAW ULP-coprocessor interrupt raw 5 1 read-only TOUCH_INT_RAW touch interrupt raw 6 1 read-only BROWN_OUT_INT_RAW brown out interrupt raw 7 1 read-only MAIN_TIMER_INT_RAW RTC main timer interrupt raw 8 1 read-only INT_ST 0x44 0x20 SLP_WAKEUP_INT_ST sleep wakeup interrupt state 0 1 read-only SLP_REJECT_INT_ST sleep reject interrupt state 1 1 read-only SDIO_IDLE_INT_ST SDIO idle interrupt state 2 1 read-only WDT_INT_ST RTC WDT interrupt state 3 1 read-only TIME_VALID_INT_ST RTC time valid interrupt state 4 1 read-only SAR_INT_ST ULP-coprocessor interrupt state 5 1 read-only TOUCH_INT_ST touch interrupt state 6 1 read-only BROWN_OUT_INT_ST brown out interrupt state 7 1 read-only MAIN_TIMER_INT_ST RTC main timer interrupt state 8 1 read-only INT_CLR 0x48 0x20 SLP_WAKEUP_INT_CLR Clear sleep wakeup interrupt state 0 1 write-only SLP_REJECT_INT_CLR Clear sleep reject interrupt state 1 1 write-only SDIO_IDLE_INT_CLR Clear SDIO idle interrupt state 2 1 write-only WDT_INT_CLR Clear RTC WDT interrupt state 3 1 write-only TIME_VALID_INT_CLR Clear RTC time valid interrupt state 4 1 write-only SAR_INT_CLR Clear ULP-coprocessor interrupt state 5 1 write-only TOUCH_INT_CLR Clear touch interrupt state 6 1 write-only BROWN_OUT_INT_CLR Clear brown out interrupt state 7 1 write-only MAIN_TIMER_INT_CLR Clear RTC main timer interrupt state 8 1 write-only STORE0 0x4C 0x20 SCRATCH0 32-bit general purpose retention register 0 32 read-write STORE1 0x50 0x20 SCRATCH1 32-bit general purpose retention register 0 32 read-write STORE2 0x54 0x20 SCRATCH2 32-bit general purpose retention register 0 32 read-write STORE3 0x58 0x20 SCRATCH3 32-bit general purpose retention register 0 32 read-write EXT_XTL_CONF 0x5C 0x20 XTL_EXT_CTR_LV 0: power down XTAL at high level 1: power down XTAL at low level 30 1 read-write XTL_EXT_CTR_EN enable control XTAL by external pads 31 1 read-write EXT_WAKEUP_CONF 0x60 0x20 EXT_WAKEUP0_LV 0: external wakeup at low level 1: external wakeup at high level 30 1 read-write EXT_WAKEUP1_LV 0: external wakeup at low level 1: external wakeup at high level 31 1 read-write SLP_REJECT_CONF 0x64 0x20 GPIO_REJECT_EN enable GPIO reject 24 1 read-write SDIO_REJECT_EN enable SDIO reject 25 1 read-write LIGHT_SLP_REJECT_EN enable reject for light sleep 26 1 read-write DEEP_SLP_REJECT_EN enable reject for deep sleep 27 1 read-write REJECT_CAUSE sleep reject cause 28 4 read-only CPU_PERIOD_CONF 0x68 0x20 CPUSEL_CONF CPU sel option 29 1 read-write CPUPERIOD_SEL CPU period sel 30 2 read-write SDIO_ACT_CONF 0x6C 0x20 SDIO_ACT_DNUM 22 10 read-write CLK_CONF 0x70 0x20 0x00002210 CK8M_DIV CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024. 4 2 read-write CK8M_DIV read-write DIV128 DIV128 0 DIV256 DIV256 1 DIV512 DIV512 2 DIV1024 DIV1024 3 ENB_CK8M disable CK8M and CK8M_D256_OUT 6 1 read-write ENB_CK8M_DIV 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256 7 1 read-write ENB_CK8M_DIV read-write CK8M_DIV_256 CK8M_DIV_256 0 CK8M CK8M 1 DIG_XTAL32K_EN enable CK_XTAL_32K for digital core (no relationship with RTC core) 8 1 read-write DIG_CLK8M_D256_EN enable CK8M_D256_OUT for digital core (no relationship with RTC core) 9 1 read-write DIG_CLK8M_EN enable CK8M for digital core (no relationship with RTC core) 10 1 read-write CK8M_DFREQ_FORCE 11 1 read-write CK8M_DIV_SEL divider = reg_ck8m_div_sel + 1 12 3 read-write XTAL_FORCE_NOGATING XTAL force no gating during sleep 15 1 read-write CK8M_FORCE_NOGATING CK8M force no gating during sleep 16 1 read-write CK8M_DFREQ CK8M_DFREQ 17 8 read-write CK8M_FORCE_PD CK8M force power down 25 1 read-write CK8M_FORCE_PU CK8M force power up 26 1 read-write SOC_CLK_SEL SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL 27 2 read-write SOC_CLK_SEL read-write XTAL XTAL 0 PLL PLL 1 CK8M CK8M 2 APLL APLL 3 FAST_CLK_RTC_SEL fast_clk_rtc sel. 0: XTAL div 4 1: CK8M 29 1 read-write FAST_CLK_RTC_SEL read-write XTAL_DIV_4 XTAL_DIV_4 0 CK8M CK8M 1 ANA_CLK_RTC_SEL slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT 30 2 read-write ANA_CLK_RTC_SEL read-write SLOW_CK SLOW_CK 0 CK_XTAL_32K CK_XTAL_32K 1 CK8M_D256_OUT CK8M_D256_OUT 2 SDIO_CONF 0x74 0x20 0x02A00000 SDIO_PD_EN power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 21 1 read-write SDIO_FORCE 1: use SW option to control SDIO_REG 0: use state machine 22 1 read-write SDIO_TIEH SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 23 1 read-write REG1P8_READY read only register for REG1P8_READY 24 1 read-only DREFL_SDIO SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 25 2 read-write DREFM_SDIO SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 27 2 read-write DREFH_SDIO SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 29 2 read-write XPD_SDIO SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1 31 1 read-write BIAS_CONF 0x78 0x20 DBG_ATTEN DBG_ATTEN 24 2 read-write ENB_SCK_XTAL ENB_SCK_XTAL 26 1 read-write INC_HEARTBEAT_REFRESH INC_HEARTBEAT_REFRESH 27 1 read-write DEC_HEARTBEAT_PERIOD DEC_HEARTBEAT_PERIOD 28 1 read-write INC_HEARTBEAT_PERIOD INC_HEARTBEAT_PERIOD 29 1 read-write DEC_HEARTBEAT_WIDTH DEC_HEARTBEAT_WIDTH 30 1 read-write RST_BIAS_I2C RST_BIAS_I2C 31 1 read-write REG 0x7C 0x20 0x29002400 SCK_DCAP_FORCE N/A 7 1 read-write DIG_DBIAS_SLP DIG_REG_DBIAS during sleep 8 3 read-write DIG_DBIAS_WAK DIG_REG_DBIAS during wakeup 11 3 read-write SCK_DCAP SCK_DCAP 14 8 read-write DBIAS_SLP RTC_DBIAS during sleep 22 3 read-write DBIAS_WAK RTC_DBIAS during wakeup 25 3 read-write DBOOST_FORCE_PD RTC_DBOOST force power down 28 1 read-write DBOOST_FORCE_PU RTC_DBOOST force power up 29 1 read-write FORCE_PD RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) 30 1 read-write FORCE_PU RTC_REG force power up 31 1 read-write PWC 0x80 0x20 0x00012925 FASTMEM_FORCE_NOISO Fast RTC memory force no ISO 0 1 read-write FASTMEM_FORCE_ISO Fast RTC memory force ISO 1 1 read-write SLOWMEM_FORCE_NOISO RTC memory force no ISO 2 1 read-write SLOWMEM_FORCE_ISO RTC memory force ISO 3 1 read-write FORCE_ISO rtc_peri force ISO 4 1 read-write FORCE_NOISO rtc_peri force no ISO 5 1 read-write FASTMEM_FOLW_CPU 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine 6 1 read-write FASTMEM_FORCE_LPD Fast RTC memory force PD 7 1 read-write FASTMEM_FORCE_LPU Fast RTC memory force no PD 8 1 read-write SLOWMEM_FOLW_CPU 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine 9 1 read-write SLOWMEM_FORCE_LPD RTC memory force PD 10 1 read-write SLOWMEM_FORCE_LPU RTC memory force no PD 11 1 read-write FASTMEM_FORCE_PD Fast RTC memory force power down 12 1 read-write FASTMEM_FORCE_PU Fast RTC memory force power up 13 1 read-write FASTMEM_PD_EN enable power down fast RTC memory in sleep 14 1 read-write SLOWMEM_FORCE_PD RTC memory force power down 15 1 read-write SLOWMEM_FORCE_PU RTC memory force power up 16 1 read-write SLOWMEM_PD_EN enable power down RTC memory in sleep 17 1 read-write FORCE_PD rtc_peri force power down 18 1 read-write FORCE_PU rtc_peri force power up 19 1 read-write PD_EN enable power down rtc_peri in sleep 20 1 read-write DIG_PWC 0x84 0x20 0x00155550 LSLP_MEM_FORCE_PD memories in digital core force PD in sleep 3 1 read-write LSLP_MEM_FORCE_PU memories in digital core force no PD in sleep 4 1 read-write ROM0_FORCE_PD ROM force power down 5 1 read-write ROM0_FORCE_PU ROM force power up 6 1 read-write INTER_RAM0_FORCE_PD internal SRAM 0 force power down 7 1 read-write INTER_RAM0_FORCE_PU internal SRAM 0 force power up 8 1 read-write INTER_RAM1_FORCE_PD internal SRAM 1 force power down 9 1 read-write INTER_RAM1_FORCE_PU internal SRAM 1 force power up 10 1 read-write INTER_RAM2_FORCE_PD internal SRAM 2 force power down 11 1 read-write INTER_RAM2_FORCE_PU internal SRAM 2 force power up 12 1 read-write INTER_RAM3_FORCE_PD internal SRAM 3 force power down 13 1 read-write INTER_RAM3_FORCE_PU internal SRAM 3 force power up 14 1 read-write INTER_RAM4_FORCE_PD internal SRAM 4 force power down 15 1 read-write INTER_RAM4_FORCE_PU internal SRAM 4 force power up 16 1 read-write WIFI_FORCE_PD wifi force power down 17 1 read-write WIFI_FORCE_PU wifi force power up 18 1 read-write DG_WRAP_FORCE_PD digital core force power down 19 1 read-write DG_WRAP_FORCE_PU digital core force power up 20 1 read-write ROM0_PD_EN enable power down ROM in sleep 24 1 read-write INTER_RAM0_PD_EN enable power down internal SRAM 0 in sleep 25 1 read-write INTER_RAM1_PD_EN enable power down internal SRAM 1 in sleep 26 1 read-write INTER_RAM2_PD_EN enable power down internal SRAM 2 in sleep 27 1 read-write INTER_RAM3_PD_EN enable power down internal SRAM 3 in sleep 28 1 read-write INTER_RAM4_PD_EN enable power down internal SRAM 4 in sleep 29 1 read-write WIFI_PD_EN enable power down wifi in sleep 30 1 read-write DG_WRAP_PD_EN enable power down digital core in sleep 31 1 read-write DIG_ISO 0x88 0x20 0xAAAA5000 FORCE_OFF 7 1 read-write FORCE_ON 8 1 read-write DG_PAD_AUTOHOLD read only register to indicate digital pad auto-hold status 9 1 read-only CLR_DG_PAD_AUTOHOLD wtite only register to clear digital pad auto-hold 10 1 write-only DG_PAD_AUTOHOLD_EN digital pad enable auto-hold 11 1 read-write DG_PAD_FORCE_NOISO digital pad force no ISO 12 1 read-write DG_PAD_FORCE_ISO digital pad force ISO 13 1 read-write DG_PAD_FORCE_UNHOLD digital pad force un-hold 14 1 read-write DG_PAD_FORCE_HOLD digital pad force hold 15 1 read-write ROM0_FORCE_ISO ROM force ISO 16 1 read-write ROM0_FORCE_NOISO ROM force no ISO 17 1 read-write INTER_RAM0_FORCE_ISO internal SRAM 0 force ISO 18 1 read-write INTER_RAM0_FORCE_NOISO internal SRAM 0 force no ISO 19 1 read-write INTER_RAM1_FORCE_ISO internal SRAM 1 force ISO 20 1 read-write INTER_RAM1_FORCE_NOISO internal SRAM 1 force no ISO 21 1 read-write INTER_RAM2_FORCE_ISO internal SRAM 2 force ISO 22 1 read-write INTER_RAM2_FORCE_NOISO internal SRAM 2 force no ISO 23 1 read-write INTER_RAM3_FORCE_ISO internal SRAM 3 force ISO 24 1 read-write INTER_RAM3_FORCE_NOISO internal SRAM 3 force no ISO 25 1 read-write INTER_RAM4_FORCE_ISO internal SRAM 4 force ISO 26 1 read-write INTER_RAM4_FORCE_NOISO internal SRAM 4 force no ISO 27 1 read-write WIFI_FORCE_ISO wifi force ISO 28 1 read-write WIFI_FORCE_NOISO wifi force no ISO 29 1 read-write DG_WRAP_FORCE_ISO digital core force ISO 30 1 read-write DG_WRAP_FORCE_NOISO digital core force no ISO 31 1 read-write WDTCONFIG0 0x8C 0x20 0x00004C80 WDT_PAUSE_IN_SLP pause WDT in sleep 7 1 read-write WDT_APPCPU_RESET_EN enable WDT reset APP CPU 8 1 read-write WDT_PROCPU_RESET_EN enable WDT reset PRO CPU 9 1 read-write WDT_FLASHBOOT_MOD_EN enable WDT in flash boot 10 1 read-write WDT_SYS_RESET_LENGTH system reset counter length 11 3 read-write WDT_CPU_RESET_LENGTH CPU reset counter length 14 3 read-write WDT_LEVEL_INT_EN N/A 17 1 read-write WDT_EDGE_INT_EN N/A 18 1 read-write WDT_STG3 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en 19 3 read-write WDT_STG2 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en 22 3 read-write WDT_STG1 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en 25 3 read-write WDT_STG0 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en 28 3 read-write WDT_EN enable RTC WDT 31 1 read-write WDTCONFIG1 0x90 0x20 0x0001F400 WDT_STG0_HOLD 0 32 read-write WDTCONFIG2 0x94 0x20 0x00013880 WDT_STG1_HOLD 0 32 read-write WDTCONFIG3 0x98 0x20 0x00000FFF WDT_STG2_HOLD 0 32 read-write WDTCONFIG4 0x9C 0x20 0x00000FFF WDT_STG3_HOLD 0 32 read-write WDTFEED 0xA0 0x20 WDT_FEED 31 1 write-only WDTWPROTECT 0xA4 0x20 0x50D83AA1 WDT_WKEY 0 32 read-write TEST_MUX 0xA8 0x20 ENT_RTC ENT_RTC 29 1 read-write DTEST_RTC DTEST_RTC 30 2 read-write SW_CPU_STALL 0xAC 0x20 SW_STALL_APPCPU_C1 {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU 20 6 read-write SW_STALL_PROCPU_C1 {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU 26 6 read-write STORE4 0xB0 0x20 SCRATCH4 32-bit general purpose retention register 0 32 read-write STORE5 0xB4 0x20 SCRATCH5 32-bit general purpose retention register 0 32 read-write STORE6 0xB8 0x20 SCRATCH6 32-bit general purpose retention register 0 32 read-write STORE7 0xBC 0x20 SCRATCH7 32-bit general purpose retention register 0 32 read-write LOW_POWER_ST 0xC0 0x20 LOW_POWER_DIAG0 0 32 read-only RDY_FOR_WAKEUP 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise 19 1 read-only DIAG1 0xC4 0x20 LOW_POWER_DIAG1 0 32 read-only HOLD_FORCE 0xC8 0x20 ADC1_HOLD_FORCE 0 1 read-write ADC2_HOLD_FORCE 1 1 read-write PDAC1_HOLD_FORCE 2 1 read-write PDAC2_HOLD_FORCE 3 1 read-write SENSE1_HOLD_FORCE 4 1 read-write SENSE2_HOLD_FORCE 5 1 read-write SENSE3_HOLD_FORCE 6 1 read-write SENSE4_HOLD_FORCE 7 1 read-write TOUCH_PAD0_HOLD_FORCE 8 1 read-write TOUCH_PAD1_HOLD_FORCE 9 1 read-write TOUCH_PAD2_HOLD_FORCE 10 1 read-write TOUCH_PAD3_HOLD_FORCE 11 1 read-write TOUCH_PAD4_HOLD_FORCE 12 1 read-write TOUCH_PAD5_HOLD_FORCE 13 1 read-write TOUCH_PAD6_HOLD_FORCE 14 1 read-write TOUCH_PAD7_HOLD_FORCE 15 1 read-write X32P_HOLD_FORCE 16 1 read-write X32N_HOLD_FORCE 17 1 read-write EXT_WAKEUP1 0xCC 0x20 SEL Bitmap to select RTC pads for ext wakeup1 0 18 read-write STATUS_CLR clear ext wakeup1 status 18 1 write-only EXT_WAKEUP1_STATUS 0xD0 0x20 EXT_WAKEUP1_STATUS ext wakeup1 status 0 18 read-only BROWN_OUT 0xD4 0x20 0x13FF0000 RTC_MEM_PID_CONF 0 8 read-write RTC_MEM_CRC_START 8 1 read-write RTC_MEM_CRC_ADDR 9 11 read-write CLOSE_FLASH_ENA enable close flash when brown out happens 14 1 read-write PD_RF_ENA enable power down RF when brown out happens 15 1 read-write RST_WAIT brown out reset wait cycles 16 10 read-write RTC_MEM_CRC_LEN 20 11 read-write RST_ENA enable brown out reset 26 1 read-write DBROWN_OUT_THRES brown out threshold 27 3 read-write ENA enable brown out 30 1 read-write DET brown out detect 31 1 read-only RTC_MEM_CRC_FINISH 31 1 read-write DATE 0x13C 0x20 0x01604280 CNTL_DATE 0 28 read-write RTCIO Peripheral RTCIO RTC_GPIO 0x3FF48400 0x0 0xCC registers OUT 0x0 0x20 DATA GPIO0~17 output value 14 18 read-write OUT_W1TS 0x4 0x20 OUT_DATA_W1TS GPIO0~17 output value write 1 to set 14 18 write-only OUT_W1TC 0x8 0x20 OUT_DATA_W1TC GPIO0~17 output value write 1 to clear 14 18 write-only ENABLE 0xC 0x20 ENABLE GPIO0~17 output enable 14 18 read-write ENABLE_W1TS 0x10 0x20 ENABLE_W1TS GPIO0~17 output enable write 1 to set 14 18 write-only ENABLE_W1TC 0x14 0x20 ENABLE_W1TC GPIO0~17 output enable write 1 to clear 14 18 write-only STATUS 0x18 0x20 INT GPIO0~17 interrupt status 14 18 read-write STATUS_W1TS 0x1C 0x20 STATUS_INT_W1TS GPIO0~17 interrupt status write 1 to set 14 18 write-only STATUS_W1TC 0x20 0x20 STATUS_INT_W1TC GPIO0~17 interrupt status write 1 to clear 14 18 write-only IN 0x24 0x20 NEXT GPIO0~17 input value 14 18 read-only 18 0x4 0-17 PIN%s 0x28 0x20 PAD_DRIVER if set to 0: normal output if set to 1: open drain 2 1 read-write INT_TYPE if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger 7 3 read-write WAKEUP_ENABLE GPIO wake up enable only available in light sleep 10 1 read-write RTC_DEBUG_SEL 0x70 0x20 DEBUG_SEL0 0 5 read-write DEBUG_SEL1 5 5 read-write DEBUG_SEL2 10 5 read-write DEBUG_SEL3 15 5 read-write DEBUG_SEL4 20 5 read-write DEBUG_12M_NO_GATING 25 1 read-write DIG_PAD_HOLD 0x74 0x20 DIG_PAD_HOLD select the digital pad hold value. 0 32 read-write HALL_SENS 0x78 0x20 HALL_PHASE Reverse phase of hall sensor 30 1 read-write XPD_HALL Power on hall sensor and connect to VP and VN 31 1 read-write SENSOR_PADS 0x7C 0x20 SENSE4_FUN_IE the input enable of the pad 4 1 read-write SENSE4_SLP_IE the input enable of the pad in sleep status 5 1 read-write SENSE4_SLP_SEL the sleep status selection signal of the pad 6 1 read-write SENSE4_FUN_SEL the functional selection signal of the pad 7 2 read-write SENSE3_FUN_IE the input enable of the pad 9 1 read-write SENSE3_SLP_IE the input enable of the pad in sleep status 10 1 read-write SENSE3_SLP_SEL the sleep status selection signal of the pad 11 1 read-write SENSE3_FUN_SEL the functional selection signal of the pad 12 2 read-write SENSE2_FUN_IE the input enable of the pad 14 1 read-write SENSE2_SLP_IE the input enable of the pad in sleep status 15 1 read-write SENSE2_SLP_SEL the sleep status selection signal of the pad 16 1 read-write SENSE2_FUN_SEL the functional selection signal of the pad 17 2 read-write SENSE1_FUN_IE the input enable of the pad 19 1 read-write SENSE1_SLP_IE the input enable of the pad in sleep status 20 1 read-write SENSE1_SLP_SEL the sleep status selection signal of the pad 21 1 read-write SENSE1_FUN_SEL the functional selection signal of the pad 22 2 read-write SENSE4_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 24 1 read-write SENSE3_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 25 1 read-write SENSE2_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 26 1 read-write SENSE1_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 27 1 read-write SENSE4_HOLD hold the current value of the output when setting the hold to Ò1Ó 28 1 read-write SENSE3_HOLD hold the current value of the output when setting the hold to Ò1Ó 29 1 read-write SENSE2_HOLD hold the current value of the output when setting the hold to Ò1Ó 30 1 read-write SENSE1_HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write ADC_PAD 0x80 0x20 ADC2_FUN_IE the input enable of the pad 18 1 read-write ADC2_SLP_IE the input enable of the pad in sleep status 19 1 read-write ADC2_SLP_SEL the sleep status selection signal of the pad 20 1 read-write ADC2_FUN_SEL the functional selection signal of the pad 21 2 read-write ADC1_FUN_IE the input enable of the pad 23 1 read-write ADC1_SLP_IE the input enable of the pad in sleep status 24 1 read-write ADC1_SLP_SEL the sleep status selection signal of the pad 25 1 read-write ADC1_FUN_SEL the functional selection signal of the pad 26 2 read-write ADC2_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 28 1 read-write ADC1_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 29 1 read-write ADC2_HOLD hold the current value of the output when setting the hold to Ò1Ó 30 1 read-write ADC1_HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write PAD_DAC1 0x84 0x20 0x80000000 PDAC1_DAC_XPD_FORCE Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 10 1 read-write PDAC1_FUN_IE the input enable of the pad 11 1 read-write PDAC1_SLP_OE the output enable of the pad in sleep status 12 1 read-write PDAC1_SLP_IE the input enable of the pad in sleep status 13 1 read-write PDAC1_SLP_SEL the sleep status selection signal of the pad 14 1 read-write PDAC1_FUN_SEL the functional selection signal of the pad 15 2 read-write PDAC1_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 17 1 read-write PDAC1_XPD_DAC Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 18 1 read-write PDAC1_DAC PAD DAC1 control code. 19 8 read-write PDAC1_RUE the pull up enable of the pad 27 1 read-write PDAC1_RDE the pull down enable of the pad 28 1 read-write PDAC1_HOLD hold the current value of the output when setting the hold to Ò1Ó 29 1 read-write PDAC1_DRV the driver strength of the pad 30 2 read-write PAD_DAC2 0x88 0x20 0x80000000 PDAC2_DAC_XPD_FORCE Power on DAC2. Usually we need to tristate PDAC2 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 10 1 read-write PDAC2_FUN_IE the input enable of the pad 11 1 read-write PDAC2_SLP_OE the output enable of the pad in sleep status 12 1 read-write PDAC2_SLP_IE the input enable of the pad in sleep status 13 1 read-write PDAC2_SLP_SEL the sleep status selection signal of the pad 14 1 read-write PDAC2_FUN_SEL the functional selection signal of the pad 15 2 read-write PDAC2_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 17 1 read-write PDAC2_XPD_DAC Power on DAC2. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 18 1 read-write PDAC2_DAC PAD DAC2 control code. 19 8 read-write PDAC2_RUE the pull up enable of the pad 27 1 read-write PDAC2_RDE the pull down enable of the pad 28 1 read-write PDAC2_HOLD hold the current value of the output when setting the hold to Ò1Ó 29 1 read-write PDAC2_DRV the driver strength of the pad 30 2 read-write XTAL_32K_PAD 0x8C 0x20 0x84100010 DBIAS_XTAL_32K 32K XTAL self-bias reference control. 1 2 read-write DRES_XTAL_32K 32K XTAL resistor bias control. 3 2 read-write X32P_FUN_IE the input enable of the pad 5 1 read-write X32P_SLP_OE the output enable of the pad in sleep status 6 1 read-write X32P_SLP_IE the input enable of the pad in sleep status 7 1 read-write X32P_SLP_SEL the sleep status selection signal of the pad 8 1 read-write X32P_FUN_SEL the functional selection signal of the pad 9 2 read-write X32N_FUN_IE the input enable of the pad 11 1 read-write X32N_SLP_OE the output enable of the pad in sleep status 12 1 read-write X32N_SLP_IE the input enable of the pad in sleep status 13 1 read-write X32N_SLP_SEL the sleep status selection signal of the pad 14 1 read-write X32N_FUN_SEL the functional selection signal of the pad 15 2 read-write X32P_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 17 1 read-write X32N_MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 18 1 read-write XPD_XTAL_32K Power up 32kHz crystal oscillator 19 1 read-write DAC_XTAL_32K 32K XTAL bias current DAC. 20 2 read-write X32P_RUE the pull up enable of the pad 22 1 read-write X32P_RDE the pull down enable of the pad 23 1 read-write X32P_HOLD hold the current value of the output when setting the hold to Ò1Ó 24 1 read-write X32P_DRV the driver strength of the pad 25 2 read-write X32N_RUE the pull up enable of the pad 27 1 read-write X32N_RDE the pull down enable of the pad 28 1 read-write X32N_HOLD hold the current value of the output when setting the hold to Ò1Ó 29 1 read-write X32N_DRV the driver strength of the pad 30 2 read-write TOUCH_CFG 0x90 0x20 0x66000000 TOUCH_DCUR touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available 23 2 read-write TOUCH_DRANGE touch sensor saw wave voltage range. 25 2 read-write TOUCH_DREFL touch sensor saw wave bottom voltage. 27 2 read-write TOUCH_DREFH touch sensor saw wave top voltage. 29 2 read-write TOUCH_XPD_BIAS touch sensor bias power on. 31 1 read-write TOUCH_PAD0 0x94 0x20 0x52000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write TOUCH_PAD1 0x98 0x20 0x4A000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD 31 1 read-write TOUCH_PAD2 0x9C 0x20 0x52000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write TOUCH_PAD3 0xA0 0x20 0x4A000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write TOUCH_PAD4 0xA4 0x20 0x52000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write TOUCH_PAD5 0xA8 0x20 0x52000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write TOUCH_PAD6 0xAC 0x20 0x4A000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write TOUCH_PAD7 0xB0 0x20 0x42000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27 12 1 read-write FUN_IE the input enable of the pad 13 1 read-write SLP_OE the output enable of the pad in sleep status 14 1 read-write SLP_IE the input enable of the pad in sleep status 15 1 read-write SLP_SEL the sleep status selection signal of the pad 16 1 read-write FUN_SEL the functional selection signal of the pad 17 2 read-write MUX_SEL Ò1Ó select the digital function Ó0Óslection the rtc function 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write RUE the pull up enable of the pad 27 1 read-write RDE the pull down enable of the pad 28 1 read-write DRV the driver strength of the pad 29 2 read-write HOLD hold the current value of the output when setting the hold to Ò1Ó 31 1 read-write TOUCH_PAD8 0xB4 0x20 0x02000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write TOUCH_PAD9 0xB8 0x20 0x02000000 TO_GPIO connect the rtc pad input to digital pad input Ó0Ó is availbale 19 1 read-write XPD touch sensor power on. 20 1 read-write TIE_OPT default touch sensor tie option. 0: tie low 1: tie high. 21 1 read-write START start touch sensor. 22 1 read-write DAC touch sensor slope control. 3-bit for each touch panel default 100. 23 3 read-write EXT_WAKEUP0 0xBC 0x20 SEL select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17 27 5 read-write XTL_EXT_CTR 0xC0 0x20 SEL select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17 27 5 read-write SAR_I2C_IO 0xC4 0x20 SAR_DEBUG_BIT_SEL 23 5 read-write SAR_I2C_SCL_SEL Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk 28 2 read-write SAR_I2C_SDA_SEL Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda 30 2 read-write DATE 0xC8 0x20 0x01603160 IO_DATE date 0 28 read-write RTC_I2C Peripheral RTC_I2C RTC_I2C 0x3FF48C00 0x0 0x3C registers SCL_LOW_PERIOD 0x0 0x20 SCL_LOW_PERIOD number of cycles that scl == 0 0 25 read-write CTRL 0x4 0x20 SDA_FORCE_OUT SDA is push-pull (1) or open-drain (0) 0 1 read-write SCL_FORCE_OUT SCL is push-pull (1) or open-drain (0) 1 1 read-write MS_MODE Master (1) or slave (0) 4 1 read-write TRANS_START Force to generate start condition 5 1 read-write TX_LSB_FIRST Send LSB first 6 1 read-write RX_LSB_FIRST Receive LSB first 7 1 read-write DEBUG_STATUS 0x8 0x20 ACK_VAL The value of an acknowledge signal on the bus 0 1 read-write SLAVE_RW When working as a slave, the value of R/W bit received 1 1 read-write TIMED_OUT Transfer has timed out 2 1 read-write ARB_LOST When working as a master, lost control of I2C bus 3 1 read-write BUS_BUSY operation is in progress 4 1 read-write SLAVE_ADDR_MATCH When working as a slave, whether address was matched 5 1 read-write BYTE_TRANS 8 bit transmit done 6 1 read-write MAIN_STATE state of the main state machine 25 3 read-write SCL_STATE state of SCL state machine 28 3 read-write TIMEOUT 0xC 0x20 TIMEOUT Maximum number of FAST_CLK cycles that the transmission can take 0 20 read-write SLAVE_ADDR 0x10 0x20 SLAVE_ADDR local slave address 0 15 read-write _10BIT Set if local slave address is 10-bit 31 1 read-write DATA 0x1C 0x20 INT_RAW 0x20 0x20 SLAVE_TRANS_COMPLETE_INT_RAW Slave accepted 1 byte and address matched 3 1 read-write ARBITRATION_LOST_INT_RAW Master lost arbitration 4 1 read-write MASTER_TRANS_COMPLETE_INT_RAW 5 1 read-write TRANS_COMPLETE_INT_RAW Stop condition has been detected interrupt raw status 6 1 read-write TIME_OUT_INT_RAW time out interrupt raw status 7 1 read-only INT_CLR 0x24 0x20 SLAVE_TRANS_COMPLETE_INT_CLR 4 1 read-write ARBITRATION_LOST_INT_CLR 5 1 read-write MASTER_TRANS_COMPLETE_INT_CLR 6 1 read-write TRANS_COMPLETE_INT_CLR 7 1 read-write TIME_OUT_INT_CLR 8 1 write-only INT_EN 0x28 0x20 INT_ST 0x2C 0x20 SDA_DUTY 0x30 0x20 SDA_DUTY Number of FAST_CLK cycles SDA will switch after falling edge of SCL 0 20 read-write SCL_HIGH_PERIOD 0x38 0x20 SCL_HIGH_PERIOD Number of FAST_CLK cycles for SCL to be high 0 20 read-write SCL_START_PERIOD 0x40 0x20 SCL_START_PERIOD Number of FAST_CLK cycles to wait before generating start condition 0 20 read-write SCL_STOP_PERIOD 0x44 0x20 SCL_STOP_PERIOD Number of FAST_CLK cycles to wait before generating stop condition 0 20 read-write CMD 0x48 0x20 VAL Command content 0 14 read-write DONE Bit is set by HW when command is done 31 1 read-write SDMMC SD/MMC Host Controller SDHOST 0x3FF68000 0x0 0xA4 registers CTRL Control register 0x0 0x20 CONTROLLER_RESET To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. 0 1 read-write FIFO_RESET To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. 1 1 read-write DMA_RESET To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. 2 1 read-write INT_ENABLE Global interrupt enable/disable bit. 0: Disable; 1: Enable. 4 1 read-write READ_WAIT For sending read-wait to SDIO cards. 6 1 read-write SEND_IRQ_RESPONSE Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. 7 1 read-write ABORT_READ_DATA After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. 8 1 read-write SEND_CCSD When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. 9 1 read-write SEND_AUTO_STOP_CCSD Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. 10 1 read-write CEATA_DEVICE_INTERRUPT_STATUS Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. 11 1 read-write CLKDIV Clock divider configuration register 0x8 0x20 CLK_DIVIDER0 Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. 0 8 read-write CLK_DIVIDER1 Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. 8 8 read-write CLK_DIVIDER2 Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. 16 8 read-write CLK_DIVIDER3 Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. 24 8 read-write CLKSRC Clock source selection register 0xC 0x20 CLKSRC Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3. 0 4 read-write CLKENA Clock enable register 0x10 0x20 CCLK_ENABLE Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled. 0 2 read-write LP_ENABLE Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled. 16 2 read-write TMOUT Data and response timeout configuration register 0x14 0x20 0xFFFFFF40 RESPONSE_TIMEOUT Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. 0 8 read-write DATA_TIMEOUT Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. 8 24 read-write CTYPE Card bus width configuration register 0x18 0x20 CARD_WIDTH4 One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit[1:0] correspond to card[1:0] respectively. 0 2 read-write CARD_WIDTH8 One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit[17:16] correspond to card[1:0] respectively. 16 2 read-write BLKSIZ Card data block size configuration register 0x1C 0x20 0x00000200 BLOCK_SIZE Block size. 0 16 read-write BYTCNT Data transfer length configuration register 0x20 0x20 0x00000200 BYTE_COUNT Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. 0 32 read-write INTMASK SDIO interrupt mask register 0x24 0x20 INT_MASK These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect. 0 16 read-write SDIO_INT_MASK SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. 16 2 read-write CMDARG Command argument data register 0x28 0x20 CMDARG Value indicates command argument to be passed to the card. 0 32 read-write CMD Command and boot configuration register 0x2C 0x20 0x20000000 INDEX Command index. 0 6 read-write RESPONSE_EXPECT 0: No response expected from card; 1: Response expected from card. 6 1 read-write RESPONSE_LENGTH 0: Short response expected from card; 1: Long response expected from card. 7 1 read-write CHECK_RESPONSE_CRC 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. 8 1 read-write DATA_EXPECTED 0: No data transfer expected; 1: Data transfer expected. 9 1 read-write READ_WRITE 0: Read from card; 1: Write to card. Don't care if no data is expected from card. 10 1 read-write TRANSFER_MODE Block data transfer command; 1: Stream data transfer command. Don't care if no data expected. 11 1 read-write SEND_AUTO_STOP 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. 12 1 read-write WAIT_PRVDATA_COMPLETE 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. 13 1 read-write STOP_ABORT_CMD 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. 14 1 read-write SEND_INITIALIZATION 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. 15 1 read-write CARD_NUMBER Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. 16 5 read-write UPDATE_CLOCK_REGISTERS_ONLY 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. 21 1 read-write READ_CEATA_DEVICE Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. 22 1 read-write CCS_EXPECTED Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. 23 1 read-write USE_HOLE Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register. 29 1 read-write START_CMD Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. 31 1 read-write RESP0 Response data register 0x30 0x20 RESPONSE0 Bit[31:0] of response. 0 32 read-only RESP1 Long response data register 0x34 0x20 RESPONSE1 Bit[63:32] of long response. 0 32 read-only RESP2 Long response data register 0x38 0x20 RESPONSE2 Bit[95:64] of long response. 0 32 read-only RESP3 Long response data register 0x3C 0x20 RESPONSE3 Bit[127:96] of long response. 0 32 read-only MINTSTS Masked interrupt status register 0x40 0x20 INT_STATUS_MSK Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect. 0 16 read-only SDIO_INTERRUPT_MSK Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). 16 2 read-only RINTSTS Raw interrupt status register 0x44 0x20 INT_STATUS_RAW Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect. 0 16 read-write SDIO_INTERRUPT_RAW Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card. 16 2 read-write STATUS SD/MMC status register 0x48 0x20 0x00000716 FIFO_RX_WATERMARK FIFO reached Receive watermark level, not qualified with data transfer. 0 1 read-only FIFO_TX_WATERMARK FIFO reached Transmit watermark level, not qualified with data transfer. 1 1 read-only FIFO_EMPTY FIFO is empty status. 2 1 read-only FIFO_FULL FIFO is full status. 3 1 read-only COMMAND_FSM_STATES Command FSM states. 0: Idle; 1: Send init sequence; 2: Send cmd start bit; 3: Send cmd tx bit; 4: Send cmd index + arg; 5: Send cmd crc7; 6: Send cmd end bit; 7: Receive resp start bit; 8: Receive resp IRQ response; 9: Receive resp tx bit; 10: Receive resp cmd idx; 11: Receive resp data; 12: Receive resp crc7; 13: Receive resp end bit; 14: Cmd path wait NCC; 15: Wait, cmd-to-response turnaround. 4 4 read-only DATA_3_STATUS Raw selected sdhost_card_data[3], checks whether card is present. 0: card not present; 1: card present. 8 1 read-only DATA_BUSY Inverted version of raw selected sdhost_card_data[0]. 0: Card data not busy; 1: Card data busy. 9 1 read-only DATA_STATE_MC_BUSY Data transmit or receive state-machine is busy. 10 1 read-only RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. 11 6 read-only FIFO_COUNT FIFO count, number of filled locations in FIFO. 17 13 read-only FIFOTH FIFO configuration register 0x4C 0x20 TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 0 12 read-write RX_WMARK FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 16 11 read-write DMA_MULTIPLE_TRANSACTION_SIZE Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. 28 3 read-write CDETECT Card detect register 0x50 0x20 CARD_DETECT_N Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. 0 2 read-only WRTPRT Card write protection (WP) status register 0x54 0x20 WRITE_PROTECT Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. 0 2 read-only TCBCNT Transferred byte count register 0x5C 0x20 TCBCNT Number of bytes transferred by CIU unit to card. 0 32 read-only TBBCNT Transferred byte count register 0x60 0x20 TBBCNT Number of bytes transferred between Host/DMA memory and BIU FIFO. 0 32 read-only DEBNCE Debounce filter time configuration register 0x64 0x20 DEBOUNCE_COUNT Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. 0 24 read-write USRID User ID (scratchpad) register 0x68 0x20 USRID User identification register, value set by user. Can also be used as a scratchpad register by user. 0 32 read-write VERID Version ID (scratchpad) register 0x6C 0x20 0x5432270A VERSIONID Hardware version register. Can also be read by fireware. 0 32 read-only HCON Hardware feature register 0x70 0x20 0x03444CC3 CARD_TYPE Hardware support SDIO and MMC. 0 1 read-only CARD_NUM Support card number is 2. 1 5 read-only BUS_TYPE Register config is APB bus. 6 1 read-only DATA_WIDTH Regisger data widht is 32. 7 3 read-only ADDR_WIDTH Register address width is 32. 10 6 read-only DMA_WIDTH DMA data witdth is 32. 18 3 read-only RAM_INDISE Inside RAM in SDMMC module. 21 1 read-only HOLD Have a hold regiser in data path . 22 1 read-only NUM_CLK_DIV Have 4 clk divider in design . 24 2 read-only UHS UHS-1 register 0x74 0x20 DDR DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe. 16 2 read-write RST_N Card reset register 0x78 0x20 0x00000001 CARD_RESET Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. 0 2 read-write BMOD Burst mode transfer configuration register 0x80 0x20 SWR Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. 0 1 read-write FB Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. 1 1 read-write DE IDMAC Enable. When set, the IDMAC is enabled. 7 1 read-write PBL Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. 8 3 read-write PLDMND Poll demand configuration register 0x84 0x20 PD Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . 0 32 write-only DBADDR Descriptor base address register 0x88 0x20 DBADDR Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. 0 32 read-write IDSTS IDMAC status register 0x8C 0x20 TI Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. 0 1 read-write RI Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. 1 1 read-write FBE Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. 2 1 read-write DU Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. 4 1 read-write CES Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. 5 1 read-write NIS Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. 8 1 read-write AIS Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. 9 1 read-write FBE_CODE Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved. 10 3 read-write FSM DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state). 13 4 read-write IDINTEN IDMAC interrupt enable register 0x90 0x20 TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. 0 1 read-write RI Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. 1 1 read-write FBE Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. 2 1 read-write DU Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. 4 1 read-write CES Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. 5 1 read-write NI Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0]: Transmit Interrupt; IDINTEN[1]: Receive Interrupt. 8 1 read-write AI Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2]: Fatal Bus Error Interrupt; IDINTEN[4]: DU Interrupt. 9 1 read-write DSCADDR Host descriptor address pointer 0x94 0x20 DSCADDR Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. 0 32 read-only BUFADDR Host buffer address pointer register 0x98 0x20 BUFADDR Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. 0 32 read-only CARDTHRCTL Card Threshold Control register 0x100 0x20 CARDRDTHREN Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled. 0 1 read-write CARDCLRINTEN Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled. 1 1 read-write CARDWRTHREN Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled. 2 1 read-write CARDTHRESHOLD The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. 16 16 read-write EMMCDDR eMMC DDR register 0x10C 0x20 HALFSTARTBIT Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle. 0 2 read-write HS400_MODE Set 1 to enable HS400 mode. 31 1 read-write ENSHIFT Enable Phase Shift register 0x110 0x20 ENABLE_SHIFT Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved. 0 4 read-write BUFFIFO CPU write and read transmit data by FIFO 0x200 0x20 BUFFIFO CPU write and read transmit data by FIFO. This register points to the current Data FIFO . 0 32 read-write CLK_EDGE_SEL SDIO control register. 0x800 0x20 0x00820200 CCLKIN_EDGE_DRV_SEL It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. 0 3 read-write CCLKIN_EDGE_SAM_SEL It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. 3 3 read-write CCLKIN_EDGE_SLF_SEL It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. 6 3 read-write CCLLKIN_EDGE_H The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. 9 4 read-write CCLLKIN_EDGE_L The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. 13 4 read-write CCLLKIN_EDGE_N The value should be equal to CCLKIN_EDGE_L. 17 4 read-write ESDIO_MODE Enable esdio mode. 21 1 read-write ESD_MODE Enable esd mode. 22 1 read-write CCLK_EN Sdio clock enable 23 1 read-write SENS Peripheral SENS SENS 0x3FF48800 0x0 0xA8 registers SAR_READ_CTRL 0x0 0x20 0x00070902 SAR1_CLK_DIV clock divider 0 8 read-write SAR1_SAMPLE_CYCLE sample cycles for SAR ADC1 8 8 read-write SAR1_SAMPLE_BIT 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width 16 2 read-write SAR1_CLK_GATED 18 1 read-write SAR1_SAMPLE_NUM 19 8 read-write SAR1_DIG_FORCE 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL 27 1 read-write SAR1_DATA_INV Invert SAR ADC1 data 28 1 read-write SAR_READ_STATUS1 0x4 0x20 SAR1_READER_STATUS 0 32 read-only SAR_MEAS_WAIT1 0x8 0x20 0x000A000A SAR_AMP_WAIT1 0 16 read-write SAR_AMP_WAIT2 16 16 read-write SAR_MEAS_WAIT2 0xC 0x20 0x0020000A FORCE_XPD_SAR_SW 0 1 read-write SAR_AMP_WAIT3 0 16 read-write FORCE_XPD_AMP 16 2 read-write FORCE_XPD_SAR 18 2 read-write SAR2_RSTB_WAIT 20 8 read-write SAR_MEAS_CTRL 0x10 0x20 0x0707338F XPD_SAR_AMP_FSM 0 4 read-write AMP_RST_FB_FSM 4 4 read-write AMP_SHORT_REF_FSM 8 4 read-write AMP_SHORT_REF_GND_FSM 12 4 read-write XPD_SAR_FSM 16 4 read-write SAR_RSTB_FSM 20 4 read-write SAR2_XPD_WAIT 24 8 read-write SAR_READ_STATUS2 0x14 0x20 SAR2_READER_STATUS 0 32 read-only ULP_CP_SLEEP_CYC0 0x18 0x20 0x000000C8 SLEEP_CYCLES_S0 sleep cycles for ULP-coprocessor timer 0 32 read-write ULP_CP_SLEEP_CYC1 0x1C 0x20 0x00000064 SLEEP_CYCLES_S1 0 32 read-write ULP_CP_SLEEP_CYC2 0x20 0x20 0x00000032 SLEEP_CYCLES_S2 0 32 read-write ULP_CP_SLEEP_CYC3 0x24 0x20 0x00000028 SLEEP_CYCLES_S3 0 32 read-write ULP_CP_SLEEP_CYC4 0x28 0x20 0x00000014 SLEEP_CYCLES_S4 0 32 read-write SAR_START_FORCE 0x2C 0x20 0x0000000F SAR1_BIT_WIDTH 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits 0 2 read-write SAR2_BIT_WIDTH 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits 2 2 read-write SAR2_EN_TEST SAR2_EN_TEST only active when reg_sar2_dig_force = 0 4 1 read-write SAR2_PWDET_CCT SAR2_PWDET_CCT PA power detector capacitance tuning. 5 3 read-write ULP_CP_FORCE_START_TOP 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer 8 1 read-write ULP_CP_START_TOP Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1 9 1 read-write SARCLK_EN 10 1 read-write PC_INIT initialized PC for ULP-coprocessor 11 11 read-write SAR2_STOP stop SAR ADC2 conversion 22 1 read-write SAR1_STOP stop SAR ADC1 conversion 23 1 read-write SAR2_PWDET_EN N/A 24 1 read-write SAR_MEM_WR_CTRL 0x30 0x20 0x00100200 MEM_WR_ADDR_INIT 0 11 read-write MEM_WR_ADDR_SIZE 11 11 read-write RTC_MEM_WR_OFFST_CLR 22 1 write-only SAR_ATTEN1 0x34 0x20 0xFFFFFFFF SAR1_ATTEN 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB 0 32 read-write SAR_ATTEN2 0x38 0x20 0xFFFFFFFF SAR2_ATTEN 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB 0 32 read-write SAR_SLAVE_ADDR1 0x3C 0x20 I2C_SLAVE_ADDR1 0 11 read-write I2C_SLAVE_ADDR0 11 11 read-write MEAS_STATUS 22 8 read-only SAR_SLAVE_ADDR2 0x40 0x20 I2C_SLAVE_ADDR3 0 11 read-write I2C_SLAVE_ADDR2 11 11 read-write SAR_SLAVE_ADDR3 0x44 0x20 I2C_SLAVE_ADDR5 0 11 read-write I2C_SLAVE_ADDR4 11 11 read-write TSENS_OUT temperature sensor data out 22 8 read-only TSENS_RDY_OUT indicate temperature sensor out ready 30 1 read-only SAR_SLAVE_ADDR4 0x48 0x20 I2C_SLAVE_ADDR7 0 11 read-write I2C_SLAVE_ADDR6 11 11 read-write I2C_RDATA I2C read data 22 8 read-only I2C_DONE indicate I2C done 30 1 read-only SAR_TSENS_CTRL 0x4C 0x20 0x00066002 TSENS_XPD_WAIT 0 12 read-write TSENS_XPD_FORCE 12 1 read-write TSENS_CLK_INV 13 1 read-write TSENS_CLK_GATED 14 1 read-write TSENS_IN_INV invert temperature sensor data 15 1 read-write TSENS_CLK_DIV temperature sensor clock divider 16 8 read-write TSENS_POWER_UP temperature sensor power up 24 1 read-write TSENS_POWER_UP_FORCE 1: dump out & power up controlled by SW 0: by FSM 25 1 read-write TSENS_DUMP_OUT temperature sensor dump out only active when reg_tsens_power_up_force = 1 26 1 read-write SAR_I2C_CTRL 0x50 0x20 SAR_I2C_CTRL I2C control data only active when reg_sar_i2c_start_force = 1 0 28 read-write SAR_I2C_START start I2C only active when reg_sar_i2c_start_force = 1 28 1 read-write SAR_I2C_START_FORCE 1: I2C started by SW 0: I2C started by FSM 29 1 read-write SAR_MEAS_START1 0x54 0x20 MEAS1_DATA_SAR SAR ADC1 data 0 16 read-only MEAS1_DONE_SAR SAR ADC1 conversion done indication 16 1 read-only MEAS1_START_SAR SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1 17 1 read-write MEAS1_START_FORCE 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor 18 1 read-write SAR1_EN_PAD SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1 19 12 read-write SAR1_EN_PAD_FORCE 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor 31 1 read-write SAR_TOUCH_CTRL1 0x58 0x20 0x02041000 TOUCH_MEAS_DELAY the meas length (in 8MHz) 0 16 read-write TOUCH_XPD_WAIT the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD 16 8 read-write TOUCH_OUT_SEL 1: when the counter is greater then the threshold the touch pad is considered as "touched" 0: when the counter is less than the threshold the touch pad is considered as "touched" 24 1 read-write TOUCH_OUT_1EN 1: wakeup interrupt is generated if SET1 is "touched" 0: wakeup interrupt is generated only if SET1 & SET2 is both "touched" 25 1 read-write XPD_HALL_FORCE 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor 26 1 read-write HALL_PHASE_FORCE 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor 27 1 read-write SAR_TOUCH_THRES1 0x5C 0x20 TOUCH_OUT_TH1 the threshold for touch pad 1 0 16 read-write TOUCH_OUT_TH0 the threshold for touch pad 0 16 16 read-write SAR_TOUCH_THRES2 0x60 0x20 TOUCH_OUT_TH3 the threshold for touch pad 3 0 16 read-write TOUCH_OUT_TH2 the threshold for touch pad 2 16 16 read-write SAR_TOUCH_THRES3 0x64 0x20 TOUCH_OUT_TH5 the threshold for touch pad 5 0 16 read-write TOUCH_OUT_TH4 the threshold for touch pad 4 16 16 read-write SAR_TOUCH_THRES4 0x68 0x20 TOUCH_OUT_TH7 the threshold for touch pad 7 0 16 read-write TOUCH_OUT_TH6 the threshold for touch pad 6 16 16 read-write SAR_TOUCH_THRES5 0x6C 0x20 TOUCH_OUT_TH9 the threshold for touch pad 9 0 16 read-write TOUCH_OUT_TH8 the threshold for touch pad 8 16 16 read-write SAR_TOUCH_OUT1 0x70 0x20 TOUCH_MEAS_OUT1 the counter for touch pad 1 0 16 read-only TOUCH_MEAS_OUT0 the counter for touch pad 0 16 16 read-only SAR_TOUCH_OUT2 0x74 0x20 TOUCH_MEAS_OUT3 the counter for touch pad 3 0 16 read-only TOUCH_MEAS_OUT2 the counter for touch pad 2 16 16 read-only SAR_TOUCH_OUT3 0x78 0x20 TOUCH_MEAS_OUT5 the counter for touch pad 5 0 16 read-only TOUCH_MEAS_OUT4 the counter for touch pad 4 16 16 read-only SAR_TOUCH_OUT4 0x7C 0x20 TOUCH_MEAS_OUT7 the counter for touch pad 7 0 16 read-only TOUCH_MEAS_OUT6 the counter for touch pad 6 16 16 read-only SAR_TOUCH_OUT5 0x80 0x20 TOUCH_MEAS_OUT9 the counter for touch pad 9 0 16 read-only TOUCH_MEAS_OUT8 the counter for touch pad 8 16 16 read-only SAR_TOUCH_CTRL2 0x84 0x20 0x00400800 TOUCH_MEAS_EN 10-bit register to indicate which pads are "touched" 0 10 read-only TOUCH_MEAS_DONE fsm set 1 to indicate touch touch meas is done 10 1 read-only TOUCH_START_FSM_EN 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers 11 1 read-write TOUCH_START_EN 1: start touch fsm valid when reg_touch_start_force is set 12 1 read-write TOUCH_START_FORCE 1: to start touch fsm by SW 0: to start touch fsm by timer 13 1 read-write TOUCH_SLEEP_CYCLES sleep cycles for timer 14 16 read-write TOUCH_MEAS_EN_CLR to clear reg_touch_meas_en 30 1 write-only SAR_TOUCH_ENABLE 0x8C 0x20 0x3FFFFFFF TOUCH_PAD_WORKEN Bitmap defining the working set during the measurement. 0 10 read-write TOUCH_PAD_OUTEN2 Bitmap defining SET2 for generating wakeup interrupt. SET2 is "touched" only if at least one of touch pad in SET2 is "touched". 10 10 read-write TOUCH_PAD_OUTEN1 Bitmap defining SET1 for generating wakeup interrupt. SET1 is "touched" only if at least one of touch pad in SET1 is "touched". 20 10 read-write SAR_READ_CTRL2 0x90 0x20 0x00070902 SAR2_CLK_DIV clock divider 0 8 read-write SAR2_SAMPLE_CYCLE sample cycles for SAR ADC2 8 8 read-write SAR2_SAMPLE_BIT 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width 16 2 read-write SAR2_CLK_GATED 18 1 read-write SAR2_SAMPLE_NUM 19 8 read-write SAR2_PWDET_FORCE 27 1 read-write SAR2_DIG_FORCE 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL 28 1 read-write SAR2_DATA_INV Invert SAR ADC2 data 29 1 read-write SAR_MEAS_START2 0x94 0x20 MEAS2_DATA_SAR SAR ADC2 data 0 16 read-only MEAS2_DONE_SAR SAR ADC2 conversion done indication 16 1 read-only MEAS2_START_SAR SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1 17 1 read-write MEAS2_START_FORCE 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor 18 1 read-write SAR2_EN_PAD SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1 19 12 read-write SAR2_EN_PAD_FORCE 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor 31 1 read-write SAR_DAC_CTRL1 0x98 0x20 SW_FSTEP frequency step for CW generator can be used to adjust the frequency 0 16 read-write SW_TONE_EN 1: enable CW generator 0: disable CW generator 16 1 read-write DEBUG_BIT_SEL 17 5 read-write DAC_DIG_FORCE 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA 22 1 read-write DAC_CLK_FORCE_LOW 1: force PDAC_CLK to low 23 1 read-write DAC_CLK_FORCE_HIGH 1: force PDAC_CLK to high 24 1 read-write DAC_CLK_INV 1: invert PDAC_CLK 25 1 read-write SAR_DAC_CTRL2 0x9C 0x20 0x03000000 DAC_DC1 DC offset for DAC1 CW generator 0 8 read-write DAC_DC2 DC offset for DAC2 CW generator 8 8 read-write DAC_SCALE1 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8 16 2 read-write DAC_SCALE2 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8 18 2 read-write DAC_INV1 00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB 20 2 read-write DAC_INV2 00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB 22 2 read-write DAC_CW_EN1 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0] 24 1 read-write DAC_CW_EN2 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0] 25 1 read-write SAR_MEAS_CTRL2 0xA0 0x20 0x00000003 SAR1_DAC_XPD_FSM 0 4 read-write SAR1_DAC_XPD_FSM_IDLE 4 1 read-write XPD_SAR_AMP_FSM_IDLE 5 1 read-write AMP_RST_FB_FSM_IDLE 6 1 read-write AMP_SHORT_REF_FSM_IDLE 7 1 read-write AMP_SHORT_REF_GND_FSM_IDLE 8 1 read-write XPD_SAR_FSM_IDLE 9 1 read-write SAR_RSTB_FSM_IDLE 10 1 read-write SAR2_RSTB_FORCE 11 2 read-write AMP_RST_FB_FORCE 13 2 read-write AMP_SHORT_REF_FORCE 15 2 read-write AMP_SHORT_REF_GND_FORCE 17 2 read-write SAR_NOUSE 0xF8 0x20 SAR_NOUSE 0 32 read-write SARDATE 0xFC 0x20 0x01605180 SAR_DATE 0 28 read-write SHA SHA (Secure Hash Algorithm) Accelerator SHA 0x3FF03000 0x0 0xC0 registers 32 0x4 TEXT_%s 0x0 0x20 TEXT SHA Message block and hash result register. 0 8 read-write SHA1_START 0x80 0x20 SHA1_START Write 1 to start an SHA-1 operation on the first message block. 0 1 write-only SHA1_CONTINUE 0x80 0x20 SHA1_CONTINUE Write 1 to continue the SHA-1 operation with subsequent blocks. 0 1 write-only SHA1_LOAD 0x88 0x20 SHA1_LOAD Write 1 to finish the SHA-1 operation to calculate the final message hash. 0 1 write-only SHA1_BUSY 0x8C 0x20 SHA1_BUSY SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. 0 1 write-only SHA256_START 0x90 0x20 SHA256_START Write 1 to start an SHA-256 operation on the first message block. 0 1 write-only SHA256_LOAD 0x90 0x20 SHA256_LOAD Write 1 to finish the SHA-256 operation to calculate the final message hash. 0 1 write-only SHA256_CONTINUE 0x94 0x20 SHA256_CONTINUE Write 1 to continue the SHA-256 operation with subsequent blocks. 0 1 write-only SHA256_BUSY 0x9C 0x20 SHA256_BUSY SHA-256 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. 0 1 read-only SHA384_START 0xA0 0x20 SHA384_START Write 1 to start an SHA-384 operation on the first message block. 0 1 write-only SHA384_CONTINUE 0xA4 0x20 SHA384_CONTINUE Write 1 to continue the SHA-384 operation with subsequent blocks. 0 1 write-only SHA384_LOAD 0xA8 0x20 SHA384_LOAD Write 1 to finish the SHA-384 operation to calculate the final message hash. 0 1 write-only SHA384_BUSY 0xAC 0x20 SHA384_BUSY SHA-384 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. 0 1 read-only SHA512_START 0xB0 0x20 SHA512_START Write 1 to start an SHA-512 operation on the first message block. 0 1 write-only SHA512_CONTINUE 0xB4 0x20 SHA512_CONTINUE Write 1 to continue the SHA-512 operation with subsequent blocks. 0 1 write-only SHA512_LOAD 0xB8 0x20 SHA512_LOAD Write 1 to finish the SHA-512 operation to calculate the final message hash. 0 1 write-only SHA512_BUSY 0xBC 0x20 SHA512_BUSY SHA-512 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle. 0 1 read-only SLC Peripheral SLC SLC 0x3FF58000 0x0 0x14C registers CONF0 0x0 0x20 0xFF3CFF30 SLC0_TX_RST 0 1 read-write SLC0_RX_RST 1 1 read-write AHBM_FIFO_RST 2 1 read-write AHBM_RST 3 1 read-write SLC0_TX_LOOP_TEST 4 1 read-write SLC0_RX_LOOP_TEST 5 1 read-write SLC0_RX_AUTO_WRBACK 6 1 read-write SLC0_RX_NO_RESTART_CLR 7 1 read-write SLC0_RXDSCR_BURST_EN 8 1 read-write SLC0_RXDATA_BURST_EN 9 1 read-write SLC0_RXLINK_AUTO_RET 10 1 read-write SLC0_TXLINK_AUTO_RET 11 1 read-write SLC0_TXDSCR_BURST_EN 12 1 read-write SLC0_TXDATA_BURST_EN 13 1 read-write SLC0_TOKEN_AUTO_CLR 14 1 read-write SLC0_TOKEN_SEL 15 1 read-write SLC1_TX_RST 16 1 read-write SLC1_RX_RST 17 1 read-write SLC0_WR_RETRY_MASK_EN 18 1 read-write SLC1_WR_RETRY_MASK_EN 19 1 read-write SLC1_TX_LOOP_TEST 20 1 read-write SLC1_RX_LOOP_TEST 21 1 read-write SLC1_RX_AUTO_WRBACK 22 1 read-write SLC1_RX_NO_RESTART_CLR 23 1 read-write SLC1_RXDSCR_BURST_EN 24 1 read-write SLC1_RXDATA_BURST_EN 25 1 read-write SLC1_RXLINK_AUTO_RET 26 1 read-write SLC1_TXLINK_AUTO_RET 27 1 read-write SLC1_TXDSCR_BURST_EN 28 1 read-write SLC1_TXDATA_BURST_EN 29 1 read-write SLC1_TOKEN_AUTO_CLR 30 1 read-write SLC1_TOKEN_SEL 31 1 read-write _0INT_RAW 0x4 0x20 FRHOST_BIT0_INT_RAW 0 1 read-only FRHOST_BIT1_INT_RAW 1 1 read-only FRHOST_BIT2_INT_RAW 2 1 read-only FRHOST_BIT3_INT_RAW 3 1 read-only FRHOST_BIT4_INT_RAW 4 1 read-only FRHOST_BIT5_INT_RAW 5 1 read-only FRHOST_BIT6_INT_RAW 6 1 read-only FRHOST_BIT7_INT_RAW 7 1 read-only SLC0_RX_START_INT_RAW 8 1 read-only SLC0_TX_START_INT_RAW 9 1 read-only SLC0_RX_UDF_INT_RAW 10 1 read-only SLC0_TX_OVF_INT_RAW 11 1 read-only SLC0_TOKEN0_1TO0_INT_RAW 12 1 read-only SLC0_TOKEN1_1TO0_INT_RAW 13 1 read-only SLC0_TX_DONE_INT_RAW 14 1 read-only SLC0_TX_SUC_EOF_INT_RAW 15 1 read-only SLC0_RX_DONE_INT_RAW 16 1 read-only SLC0_RX_EOF_INT_RAW 17 1 read-only SLC0_TOHOST_INT_RAW 18 1 read-only SLC0_TX_DSCR_ERR_INT_RAW 19 1 read-only SLC0_RX_DSCR_ERR_INT_RAW 20 1 read-only SLC0_TX_DSCR_EMPTY_INT_RAW 21 1 read-only SLC0_HOST_RD_ACK_INT_RAW 22 1 read-only SLC0_WR_RETRY_DONE_INT_RAW 23 1 read-only SLC0_TX_ERR_EOF_INT_RAW 24 1 read-only CMD_DTC_INT_RAW 25 1 read-only SLC0_RX_QUICK_EOF_INT_RAW 26 1 read-only _0INT_ST 0x8 0x20 FRHOST_BIT0_INT_ST 0 1 read-only FRHOST_BIT1_INT_ST 1 1 read-only FRHOST_BIT2_INT_ST 2 1 read-only FRHOST_BIT3_INT_ST 3 1 read-only FRHOST_BIT4_INT_ST 4 1 read-only FRHOST_BIT5_INT_ST 5 1 read-only FRHOST_BIT6_INT_ST 6 1 read-only FRHOST_BIT7_INT_ST 7 1 read-only SLC0_RX_START_INT_ST 8 1 read-only SLC0_TX_START_INT_ST 9 1 read-only SLC0_RX_UDF_INT_ST 10 1 read-only SLC0_TX_OVF_INT_ST 11 1 read-only SLC0_TOKEN0_1TO0_INT_ST 12 1 read-only SLC0_TOKEN1_1TO0_INT_ST 13 1 read-only SLC0_TX_DONE_INT_ST 14 1 read-only SLC0_TX_SUC_EOF_INT_ST 15 1 read-only SLC0_RX_DONE_INT_ST 16 1 read-only SLC0_RX_EOF_INT_ST 17 1 read-only SLC0_TOHOST_INT_ST 18 1 read-only SLC0_TX_DSCR_ERR_INT_ST 19 1 read-only SLC0_RX_DSCR_ERR_INT_ST 20 1 read-only SLC0_TX_DSCR_EMPTY_INT_ST 21 1 read-only SLC0_HOST_RD_ACK_INT_ST 22 1 read-only SLC0_WR_RETRY_DONE_INT_ST 23 1 read-only SLC0_TX_ERR_EOF_INT_ST 24 1 read-only CMD_DTC_INT_ST 25 1 read-only SLC0_RX_QUICK_EOF_INT_ST 26 1 read-only _0INT_ENA 0xC 0x20 FRHOST_BIT0_INT_ENA 0 1 read-write FRHOST_BIT1_INT_ENA 1 1 read-write FRHOST_BIT2_INT_ENA 2 1 read-write FRHOST_BIT3_INT_ENA 3 1 read-write FRHOST_BIT4_INT_ENA 4 1 read-write FRHOST_BIT5_INT_ENA 5 1 read-write FRHOST_BIT6_INT_ENA 6 1 read-write FRHOST_BIT7_INT_ENA 7 1 read-write SLC0_RX_START_INT_ENA 8 1 read-write SLC0_TX_START_INT_ENA 9 1 read-write SLC0_RX_UDF_INT_ENA 10 1 read-write SLC0_TX_OVF_INT_ENA 11 1 read-write SLC0_TOKEN0_1TO0_INT_ENA 12 1 read-write SLC0_TOKEN1_1TO0_INT_ENA 13 1 read-write SLC0_TX_DONE_INT_ENA 14 1 read-write SLC0_TX_SUC_EOF_INT_ENA 15 1 read-write SLC0_RX_DONE_INT_ENA 16 1 read-write SLC0_RX_EOF_INT_ENA 17 1 read-write SLC0_TOHOST_INT_ENA 18 1 read-write SLC0_TX_DSCR_ERR_INT_ENA 19 1 read-write SLC0_RX_DSCR_ERR_INT_ENA 20 1 read-write SLC0_TX_DSCR_EMPTY_INT_ENA 21 1 read-write SLC0_HOST_RD_ACK_INT_ENA 22 1 read-write SLC0_WR_RETRY_DONE_INT_ENA 23 1 read-write SLC0_TX_ERR_EOF_INT_ENA 24 1 read-write CMD_DTC_INT_ENA 25 1 read-write SLC0_RX_QUICK_EOF_INT_ENA 26 1 read-write _0INT_CLR 0x10 0x20 FRHOST_BIT0_INT_CLR 0 1 write-only FRHOST_BIT1_INT_CLR 1 1 write-only FRHOST_BIT2_INT_CLR 2 1 write-only FRHOST_BIT3_INT_CLR 3 1 write-only FRHOST_BIT4_INT_CLR 4 1 write-only FRHOST_BIT5_INT_CLR 5 1 write-only FRHOST_BIT6_INT_CLR 6 1 write-only FRHOST_BIT7_INT_CLR 7 1 write-only SLC0_RX_START_INT_CLR 8 1 write-only SLC0_TX_START_INT_CLR 9 1 write-only SLC0_RX_UDF_INT_CLR 10 1 write-only SLC0_TX_OVF_INT_CLR 11 1 write-only SLC0_TOKEN0_1TO0_INT_CLR 12 1 write-only SLC0_TOKEN1_1TO0_INT_CLR 13 1 write-only SLC0_TX_DONE_INT_CLR 14 1 write-only SLC0_TX_SUC_EOF_INT_CLR 15 1 write-only SLC0_RX_DONE_INT_CLR 16 1 write-only SLC0_RX_EOF_INT_CLR 17 1 write-only SLC0_TOHOST_INT_CLR 18 1 write-only SLC0_TX_DSCR_ERR_INT_CLR 19 1 write-only SLC0_RX_DSCR_ERR_INT_CLR 20 1 write-only SLC0_TX_DSCR_EMPTY_INT_CLR 21 1 write-only SLC0_HOST_RD_ACK_INT_CLR 22 1 write-only SLC0_WR_RETRY_DONE_INT_CLR 23 1 write-only SLC0_TX_ERR_EOF_INT_CLR 24 1 write-only CMD_DTC_INT_CLR 25 1 write-only SLC0_RX_QUICK_EOF_INT_CLR 26 1 write-only _1INT_RAW 0x14 0x20 FRHOST_BIT8_INT_RAW 0 1 read-only FRHOST_BIT9_INT_RAW 1 1 read-only FRHOST_BIT10_INT_RAW 2 1 read-only FRHOST_BIT11_INT_RAW 3 1 read-only FRHOST_BIT12_INT_RAW 4 1 read-only FRHOST_BIT13_INT_RAW 5 1 read-only FRHOST_BIT14_INT_RAW 6 1 read-only FRHOST_BIT15_INT_RAW 7 1 read-only SLC1_RX_START_INT_RAW 8 1 read-only SLC1_TX_START_INT_RAW 9 1 read-only SLC1_RX_UDF_INT_RAW 10 1 read-only SLC1_TX_OVF_INT_RAW 11 1 read-only SLC1_TOKEN0_1TO0_INT_RAW 12 1 read-only SLC1_TOKEN1_1TO0_INT_RAW 13 1 read-only SLC1_TX_DONE_INT_RAW 14 1 read-only SLC1_TX_SUC_EOF_INT_RAW 15 1 read-only SLC1_RX_DONE_INT_RAW 16 1 read-only SLC1_RX_EOF_INT_RAW 17 1 read-only SLC1_TOHOST_INT_RAW 18 1 read-only SLC1_TX_DSCR_ERR_INT_RAW 19 1 read-only SLC1_RX_DSCR_ERR_INT_RAW 20 1 read-only SLC1_TX_DSCR_EMPTY_INT_RAW 21 1 read-only SLC1_HOST_RD_ACK_INT_RAW 22 1 read-only SLC1_WR_RETRY_DONE_INT_RAW 23 1 read-only SLC1_TX_ERR_EOF_INT_RAW 24 1 read-only _1INT_ST 0x18 0x20 FRHOST_BIT8_INT_ST 0 1 read-only FRHOST_BIT9_INT_ST 1 1 read-only FRHOST_BIT10_INT_ST 2 1 read-only FRHOST_BIT11_INT_ST 3 1 read-only FRHOST_BIT12_INT_ST 4 1 read-only FRHOST_BIT13_INT_ST 5 1 read-only FRHOST_BIT14_INT_ST 6 1 read-only FRHOST_BIT15_INT_ST 7 1 read-only SLC1_RX_START_INT_ST 8 1 read-only SLC1_TX_START_INT_ST 9 1 read-only SLC1_RX_UDF_INT_ST 10 1 read-only SLC1_TX_OVF_INT_ST 11 1 read-only SLC1_TOKEN0_1TO0_INT_ST 12 1 read-only SLC1_TOKEN1_1TO0_INT_ST 13 1 read-only SLC1_TX_DONE_INT_ST 14 1 read-only SLC1_TX_SUC_EOF_INT_ST 15 1 read-only SLC1_RX_DONE_INT_ST 16 1 read-only SLC1_RX_EOF_INT_ST 17 1 read-only SLC1_TOHOST_INT_ST 18 1 read-only SLC1_TX_DSCR_ERR_INT_ST 19 1 read-only SLC1_RX_DSCR_ERR_INT_ST 20 1 read-only SLC1_TX_DSCR_EMPTY_INT_ST 21 1 read-only SLC1_HOST_RD_ACK_INT_ST 22 1 read-only SLC1_WR_RETRY_DONE_INT_ST 23 1 read-only SLC1_TX_ERR_EOF_INT_ST 24 1 read-only _1INT_ENA 0x1C 0x20 FRHOST_BIT8_INT_ENA 0 1 read-write FRHOST_BIT9_INT_ENA 1 1 read-write FRHOST_BIT10_INT_ENA 2 1 read-write FRHOST_BIT11_INT_ENA 3 1 read-write FRHOST_BIT12_INT_ENA 4 1 read-write FRHOST_BIT13_INT_ENA 5 1 read-write FRHOST_BIT14_INT_ENA 6 1 read-write FRHOST_BIT15_INT_ENA 7 1 read-write SLC1_RX_START_INT_ENA 8 1 read-write SLC1_TX_START_INT_ENA 9 1 read-write SLC1_RX_UDF_INT_ENA 10 1 read-write SLC1_TX_OVF_INT_ENA 11 1 read-write SLC1_TOKEN0_1TO0_INT_ENA 12 1 read-write SLC1_TOKEN1_1TO0_INT_ENA 13 1 read-write SLC1_TX_DONE_INT_ENA 14 1 read-write SLC1_TX_SUC_EOF_INT_ENA 15 1 read-write SLC1_RX_DONE_INT_ENA 16 1 read-write SLC1_RX_EOF_INT_ENA 17 1 read-write SLC1_TOHOST_INT_ENA 18 1 read-write SLC1_TX_DSCR_ERR_INT_ENA 19 1 read-write SLC1_RX_DSCR_ERR_INT_ENA 20 1 read-write SLC1_TX_DSCR_EMPTY_INT_ENA 21 1 read-write SLC1_HOST_RD_ACK_INT_ENA 22 1 read-write SLC1_WR_RETRY_DONE_INT_ENA 23 1 read-write SLC1_TX_ERR_EOF_INT_ENA 24 1 read-write _1INT_CLR 0x20 0x20 FRHOST_BIT8_INT_CLR 0 1 write-only FRHOST_BIT9_INT_CLR 1 1 write-only FRHOST_BIT10_INT_CLR 2 1 write-only FRHOST_BIT11_INT_CLR 3 1 write-only FRHOST_BIT12_INT_CLR 4 1 write-only FRHOST_BIT13_INT_CLR 5 1 write-only FRHOST_BIT14_INT_CLR 6 1 write-only FRHOST_BIT15_INT_CLR 7 1 write-only SLC1_RX_START_INT_CLR 8 1 write-only SLC1_TX_START_INT_CLR 9 1 write-only SLC1_RX_UDF_INT_CLR 10 1 write-only SLC1_TX_OVF_INT_CLR 11 1 write-only SLC1_TOKEN0_1TO0_INT_CLR 12 1 write-only SLC1_TOKEN1_1TO0_INT_CLR 13 1 write-only SLC1_TX_DONE_INT_CLR 14 1 write-only SLC1_TX_SUC_EOF_INT_CLR 15 1 write-only SLC1_RX_DONE_INT_CLR 16 1 write-only SLC1_RX_EOF_INT_CLR 17 1 write-only SLC1_TOHOST_INT_CLR 18 1 write-only SLC1_TX_DSCR_ERR_INT_CLR 19 1 write-only SLC1_RX_DSCR_ERR_INT_CLR 20 1 write-only SLC1_TX_DSCR_EMPTY_INT_CLR 21 1 write-only SLC1_HOST_RD_ACK_INT_CLR 22 1 write-only SLC1_WR_RETRY_DONE_INT_CLR 23 1 write-only SLC1_TX_ERR_EOF_INT_CLR 24 1 write-only RX_STATUS 0x24 0x20 0x00020002 SLC0_RX_FULL 0 1 read-only SLC0_RX_EMPTY 1 1 read-only SLC1_RX_FULL 16 1 read-only SLC1_RX_EMPTY 17 1 read-only _0RXFIFO_PUSH 0x28 0x20 SLC0_RXFIFO_WDATA 0 9 read-write SLC0_RXFIFO_PUSH 16 1 read-write _1RXFIFO_PUSH 0x2C 0x20 SLC1_RXFIFO_WDATA 0 9 read-write SLC1_RXFIFO_PUSH 16 1 read-write TX_STATUS 0x30 0x20 0x00020002 SLC0_TX_FULL 0 1 read-only SLC0_TX_EMPTY 1 1 read-only SLC1_TX_FULL 16 1 read-only SLC1_TX_EMPTY 17 1 read-only _0TXFIFO_POP 0x34 0x20 SLC0_TXFIFO_RDATA 0 11 read-only SLC0_TXFIFO_POP 16 1 read-write _1TXFIFO_POP 0x38 0x20 SLC1_TXFIFO_RDATA 0 11 read-only SLC1_TXFIFO_POP 16 1 read-write _0RX_LINK 0x3C 0x20 SLC0_RXLINK_ADDR 0 20 read-write SLC0_RXLINK_STOP 28 1 read-write SLC0_RXLINK_START 29 1 read-write SLC0_RXLINK_RESTART 30 1 read-write SLC0_RXLINK_PARK 31 1 read-only _0TX_LINK 0x40 0x20 SLC0_TXLINK_ADDR 0 20 read-write SLC0_TXLINK_STOP 28 1 read-write SLC0_TXLINK_START 29 1 read-write SLC0_TXLINK_RESTART 30 1 read-write SLC0_TXLINK_PARK 31 1 read-only _1RX_LINK 0x44 0x20 0x00100000 SLC1_RXLINK_ADDR 0 20 read-write SLC1_BT_PACKET 20 1 read-write SLC1_RXLINK_STOP 28 1 read-write SLC1_RXLINK_START 29 1 read-write SLC1_RXLINK_RESTART 30 1 read-write SLC1_RXLINK_PARK 31 1 read-only _1TX_LINK 0x48 0x20 SLC1_TXLINK_ADDR 0 20 read-write SLC1_TXLINK_STOP 28 1 read-write SLC1_TXLINK_START 29 1 read-write SLC1_TXLINK_RESTART 30 1 read-write SLC1_TXLINK_PARK 31 1 read-only INTVEC_TOHOST 0x4C 0x20 SLC0_TOHOST_INTVEC 0 8 write-only SLC1_TOHOST_INTVEC 16 8 write-only _0TOKEN0 0x50 0x20 SLC0_TOKEN0_WDATA 0 12 write-only SLC0_TOKEN0_WR 12 1 write-only SLC0_TOKEN0_INC 13 1 write-only SLC0_TOKEN0_INC_MORE 14 1 write-only SLC0_TOKEN0 16 12 read-only _0TOKEN1 0x54 0x20 SLC0_TOKEN1_WDATA 0 12 write-only SLC0_TOKEN1_WR 12 1 write-only SLC0_TOKEN1_INC 13 1 write-only SLC0_TOKEN1_INC_MORE 14 1 write-only SLC0_TOKEN1 16 12 read-only _1TOKEN0 0x58 0x20 SLC1_TOKEN0_WDATA 0 12 write-only SLC1_TOKEN0_WR 12 1 write-only SLC1_TOKEN0_INC 13 1 write-only SLC1_TOKEN0_INC_MORE 14 1 write-only SLC1_TOKEN0 16 12 read-only _1TOKEN1 0x5C 0x20 SLC1_TOKEN1_WDATA 0 12 write-only SLC1_TOKEN1_WR 12 1 write-only SLC1_TOKEN1_INC 13 1 write-only SLC1_TOKEN1_INC_MORE 14 1 write-only SLC1_TOKEN1 16 12 read-only CONF1 0x60 0x20 0x00300078 SLC0_CHECK_OWNER 0 1 read-write SLC0_TX_CHECK_SUM_EN 1 1 read-write SLC0_RX_CHECK_SUM_EN 2 1 read-write CMD_HOLD_EN 3 1 read-write SLC0_LEN_AUTO_CLR 4 1 read-write SLC0_TX_STITCH_EN 5 1 read-write SLC0_RX_STITCH_EN 6 1 read-write SLC1_CHECK_OWNER 16 1 read-write SLC1_TX_CHECK_SUM_EN 17 1 read-write SLC1_RX_CHECK_SUM_EN 18 1 read-write HOST_INT_LEVEL_SEL 19 1 read-write SLC1_TX_STITCH_EN 20 1 read-write SLC1_RX_STITCH_EN 21 1 read-write CLK_EN 22 1 read-write _0_STATE0 0x64 0x20 SLC0_STATE0 0 32 read-only _0_STATE1 0x68 0x20 SLC0_STATE1 0 32 read-only _1_STATE0 0x6C 0x20 SLC1_STATE0 0 32 read-only _1_STATE1 0x70 0x20 SLC1_STATE1 0 32 read-only BRIDGE_CONF 0x74 0x20 0x000A7720 TXEOF_ENA 0 6 read-write FIFO_MAP_ENA 8 4 read-write SLC0_TX_DUMMY_MODE 12 1 read-write HDA_MAP_128K 13 1 read-write SLC1_TX_DUMMY_MODE 14 1 read-write TX_PUSH_IDLE_NUM 16 16 read-write _0_TO_EOF_DES_ADDR 0x78 0x20 SLC0_TO_EOF_DES_ADDR 0 32 read-only _0_TX_EOF_DES_ADDR 0x7C 0x20 SLC0_TX_SUC_EOF_DES_ADDR 0 32 read-only _0_TO_EOF_BFR_DES_ADDR 0x80 0x20 SLC0_TO_EOF_BFR_DES_ADDR 0 32 read-only _1_TO_EOF_DES_ADDR 0x84 0x20 SLC1_TO_EOF_DES_ADDR 0 32 read-only _1_TX_EOF_DES_ADDR 0x88 0x20 SLC1_TX_SUC_EOF_DES_ADDR 0 32 read-only _1_TO_EOF_BFR_DES_ADDR 0x8C 0x20 SLC1_TO_EOF_BFR_DES_ADDR 0 32 read-only AHB_TEST 0x90 0x20 AHB_TESTMODE 0 3 read-write AHB_TESTADDR 4 2 read-write SDIO_ST 0x94 0x20 CMD_ST 0 3 read-only FUNC_ST 4 4 read-only SDIO_WAKEUP 8 1 read-only BUS_ST 12 3 read-only FUNC1_ACC_STATE 16 5 read-only FUNC2_ACC_STATE 24 5 read-only RX_DSCR_CONF 0x98 0x20 0x101B101A SLC0_TOKEN_NO_REPLACE 0 1 read-write SLC0_INFOR_NO_REPLACE 1 1 read-write SLC0_RX_FILL_MODE 2 1 read-write SLC0_RX_EOF_MODE 3 1 read-write SLC0_RX_FILL_EN 4 1 read-write SLC0_RD_RETRY_THRESHOLD 5 11 read-write SLC1_TOKEN_NO_REPLACE 16 1 read-write SLC1_INFOR_NO_REPLACE 17 1 read-write SLC1_RX_FILL_MODE 18 1 read-write SLC1_RX_EOF_MODE 19 1 read-write SLC1_RX_FILL_EN 20 1 read-write SLC1_RD_RETRY_THRESHOLD 21 11 read-write _0_TXLINK_DSCR 0x9C 0x20 SLC0_TXLINK_DSCR 0 32 read-only _0_TXLINK_DSCR_BF0 0xA0 0x20 SLC0_TXLINK_DSCR_BF0 0 32 read-only _0_TXLINK_DSCR_BF1 0xA4 0x20 SLC0_TXLINK_DSCR_BF1 0 32 read-only _0_RXLINK_DSCR 0xA8 0x20 SLC0_RXLINK_DSCR 0 32 read-only _0_RXLINK_DSCR_BF0 0xAC 0x20 SLC0_RXLINK_DSCR_BF0 0 32 read-only _0_RXLINK_DSCR_BF1 0xB0 0x20 SLC0_RXLINK_DSCR_BF1 0 32 read-only _1_TXLINK_DSCR 0xB4 0x20 SLC1_TXLINK_DSCR 0 32 read-only _1_TXLINK_DSCR_BF0 0xB8 0x20 SLC1_TXLINK_DSCR_BF0 0 32 read-only _1_TXLINK_DSCR_BF1 0xBC 0x20 SLC1_TXLINK_DSCR_BF1 0 32 read-only _1_RXLINK_DSCR 0xC0 0x20 SLC1_RXLINK_DSCR 0 32 read-only _1_RXLINK_DSCR_BF0 0xC4 0x20 SLC1_RXLINK_DSCR_BF0 0 32 read-only _1_RXLINK_DSCR_BF1 0xC8 0x20 SLC1_RXLINK_DSCR_BF1 0 32 read-only _0_TX_ERREOF_DES_ADDR 0xCC 0x20 SLC0_TX_ERR_EOF_DES_ADDR 0 32 read-only _1_TX_ERREOF_DES_ADDR 0xD0 0x20 SLC1_TX_ERR_EOF_DES_ADDR 0 32 read-only TOKEN_LAT 0xD4 0x20 SLC0_TOKEN 0 12 read-only SLC1_TOKEN 16 12 read-only TX_DSCR_CONF 0xD8 0x20 0x00000080 WR_RETRY_THRESHOLD 0 11 read-write CMD_INFOR0 0xDC 0x20 CMD_CONTENT0 0 32 read-only CMD_INFOR1 0xE0 0x20 CMD_CONTENT1 0 32 read-only _0_LEN_CONF 0xE4 0x20 SLC0_LEN_WDATA 0 20 write-only SLC0_LEN_WR 20 1 write-only SLC0_LEN_INC 21 1 write-only SLC0_LEN_INC_MORE 22 1 write-only SLC0_RX_PACKET_LOAD_EN 23 1 read-write SLC0_TX_PACKET_LOAD_EN 24 1 read-write SLC0_RX_GET_USED_DSCR 25 1 write-only SLC0_TX_GET_USED_DSCR 26 1 write-only SLC0_RX_NEW_PKT_IND 27 1 read-only SLC0_TX_NEW_PKT_IND 28 1 read-only _0_LENGTH 0xE8 0x20 SLC0_LEN 0 20 read-only _0_TXPKT_H_DSCR 0xEC 0x20 SLC0_TX_PKT_H_DSCR_ADDR 0 32 read-write _0_TXPKT_E_DSCR 0xF0 0x20 SLC0_TX_PKT_E_DSCR_ADDR 0 32 read-write _0_RXPKT_H_DSCR 0xF4 0x20 SLC0_RX_PKT_H_DSCR_ADDR 0 32 read-write _0_RXPKT_E_DSCR 0xF8 0x20 SLC0_RX_PKT_E_DSCR_ADDR 0 32 read-write _0_TXPKTU_H_DSCR 0xFC 0x20 SLC0_TX_PKT_START_DSCR_ADDR 0 32 read-only _0_TXPKTU_E_DSCR 0x100 0x20 SLC0_TX_PKT_END_DSCR_ADDR 0 32 read-only _0_RXPKTU_H_DSCR 0x104 0x20 SLC0_RX_PKT_START_DSCR_ADDR 0 32 read-only _0_RXPKTU_E_DSCR 0x108 0x20 SLC0_RX_PKT_END_DSCR_ADDR 0 32 read-only SEQ_POSITION 0x114 0x20 0x00000509 SLC0_SEQ_POSITION 0 8 read-write SLC1_SEQ_POSITION 8 8 read-write _0_DSCR_REC_CONF 0x118 0x20 0x000003FF SLC0_RX_DSCR_REC_LIM 0 10 read-write SDIO_CRC_ST0 0x11C 0x20 DAT0_CRC_ERR_CNT 0 8 read-only DAT1_CRC_ERR_CNT 8 8 read-only DAT2_CRC_ERR_CNT 16 8 read-only DAT3_CRC_ERR_CNT 24 8 read-only SDIO_CRC_ST1 0x120 0x20 CMD_CRC_ERR_CNT 0 8 read-only ERR_CNT_CLR 31 1 read-write _0_EOF_START_DES 0x124 0x20 SLC0_EOF_START_DES_ADDR 0 32 read-only _0_PUSH_DSCR_ADDR 0x128 0x20 SLC0_RX_PUSH_DSCR_ADDR 0 32 read-only _0_DONE_DSCR_ADDR 0x12C 0x20 SLC0_RX_DONE_DSCR_ADDR 0 32 read-only _0_SUB_START_DES 0x130 0x20 SLC0_SUB_PAC_START_DSCR_ADDR 0 32 read-only _0_DSCR_CNT 0x134 0x20 SLC0_RX_DSCR_CNT_LAT 0 10 read-only SLC0_RX_GET_EOF_OCC 16 1 read-only _0_LEN_LIM_CONF 0x138 0x20 0x00005400 SLC0_LEN_LIM 0 20 read-write _0INT_ST1 0x13C 0x20 FRHOST_BIT0_INT_ST1 0 1 read-only FRHOST_BIT1_INT_ST1 1 1 read-only FRHOST_BIT2_INT_ST1 2 1 read-only FRHOST_BIT3_INT_ST1 3 1 read-only FRHOST_BIT4_INT_ST1 4 1 read-only FRHOST_BIT5_INT_ST1 5 1 read-only FRHOST_BIT6_INT_ST1 6 1 read-only FRHOST_BIT7_INT_ST1 7 1 read-only SLC0_RX_START_INT_ST1 8 1 read-only SLC0_TX_START_INT_ST1 9 1 read-only SLC0_RX_UDF_INT_ST1 10 1 read-only SLC0_TX_OVF_INT_ST1 11 1 read-only SLC0_TOKEN0_1TO0_INT_ST1 12 1 read-only SLC0_TOKEN1_1TO0_INT_ST1 13 1 read-only SLC0_TX_DONE_INT_ST1 14 1 read-only SLC0_TX_SUC_EOF_INT_ST1 15 1 read-only SLC0_RX_DONE_INT_ST1 16 1 read-only SLC0_RX_EOF_INT_ST1 17 1 read-only SLC0_TOHOST_INT_ST1 18 1 read-only SLC0_TX_DSCR_ERR_INT_ST1 19 1 read-only SLC0_RX_DSCR_ERR_INT_ST1 20 1 read-only SLC0_TX_DSCR_EMPTY_INT_ST1 21 1 read-only SLC0_HOST_RD_ACK_INT_ST1 22 1 read-only SLC0_WR_RETRY_DONE_INT_ST1 23 1 read-only SLC0_TX_ERR_EOF_INT_ST1 24 1 read-only CMD_DTC_INT_ST1 25 1 read-only SLC0_RX_QUICK_EOF_INT_ST1 26 1 read-only _0INT_ENA1 0x140 0x20 FRHOST_BIT0_INT_ENA1 0 1 read-write FRHOST_BIT1_INT_ENA1 1 1 read-write FRHOST_BIT2_INT_ENA1 2 1 read-write FRHOST_BIT3_INT_ENA1 3 1 read-write FRHOST_BIT4_INT_ENA1 4 1 read-write FRHOST_BIT5_INT_ENA1 5 1 read-write FRHOST_BIT6_INT_ENA1 6 1 read-write FRHOST_BIT7_INT_ENA1 7 1 read-write SLC0_RX_START_INT_ENA1 8 1 read-write SLC0_TX_START_INT_ENA1 9 1 read-write SLC0_RX_UDF_INT_ENA1 10 1 read-write SLC0_TX_OVF_INT_ENA1 11 1 read-write SLC0_TOKEN0_1TO0_INT_ENA1 12 1 read-write SLC0_TOKEN1_1TO0_INT_ENA1 13 1 read-write SLC0_TX_DONE_INT_ENA1 14 1 read-write SLC0_TX_SUC_EOF_INT_ENA1 15 1 read-write SLC0_RX_DONE_INT_ENA1 16 1 read-write SLC0_RX_EOF_INT_ENA1 17 1 read-write SLC0_TOHOST_INT_ENA1 18 1 read-write SLC0_TX_DSCR_ERR_INT_ENA1 19 1 read-write SLC0_RX_DSCR_ERR_INT_ENA1 20 1 read-write SLC0_TX_DSCR_EMPTY_INT_ENA1 21 1 read-write SLC0_HOST_RD_ACK_INT_ENA1 22 1 read-write SLC0_WR_RETRY_DONE_INT_ENA1 23 1 read-write SLC0_TX_ERR_EOF_INT_ENA1 24 1 read-write CMD_DTC_INT_ENA1 25 1 read-write SLC0_RX_QUICK_EOF_INT_ENA1 26 1 read-write _1INT_ST1 0x144 0x20 FRHOST_BIT8_INT_ST1 0 1 read-only FRHOST_BIT9_INT_ST1 1 1 read-only FRHOST_BIT10_INT_ST1 2 1 read-only FRHOST_BIT11_INT_ST1 3 1 read-only FRHOST_BIT12_INT_ST1 4 1 read-only FRHOST_BIT13_INT_ST1 5 1 read-only FRHOST_BIT14_INT_ST1 6 1 read-only FRHOST_BIT15_INT_ST1 7 1 read-only SLC1_RX_START_INT_ST1 8 1 read-only SLC1_TX_START_INT_ST1 9 1 read-only SLC1_RX_UDF_INT_ST1 10 1 read-only SLC1_TX_OVF_INT_ST1 11 1 read-only SLC1_TOKEN0_1TO0_INT_ST1 12 1 read-only SLC1_TOKEN1_1TO0_INT_ST1 13 1 read-only SLC1_TX_DONE_INT_ST1 14 1 read-only SLC1_TX_SUC_EOF_INT_ST1 15 1 read-only SLC1_RX_DONE_INT_ST1 16 1 read-only SLC1_RX_EOF_INT_ST1 17 1 read-only SLC1_TOHOST_INT_ST1 18 1 read-only SLC1_TX_DSCR_ERR_INT_ST1 19 1 read-only SLC1_RX_DSCR_ERR_INT_ST1 20 1 read-only SLC1_TX_DSCR_EMPTY_INT_ST1 21 1 read-only SLC1_HOST_RD_ACK_INT_ST1 22 1 read-only SLC1_WR_RETRY_DONE_INT_ST1 23 1 read-only SLC1_TX_ERR_EOF_INT_ST1 24 1 read-only _1INT_ENA1 0x148 0x20 FRHOST_BIT8_INT_ENA1 0 1 read-write FRHOST_BIT9_INT_ENA1 1 1 read-write FRHOST_BIT10_INT_ENA1 2 1 read-write FRHOST_BIT11_INT_ENA1 3 1 read-write FRHOST_BIT12_INT_ENA1 4 1 read-write FRHOST_BIT13_INT_ENA1 5 1 read-write FRHOST_BIT14_INT_ENA1 6 1 read-write FRHOST_BIT15_INT_ENA1 7 1 read-write SLC1_RX_START_INT_ENA1 8 1 read-write SLC1_TX_START_INT_ENA1 9 1 read-write SLC1_RX_UDF_INT_ENA1 10 1 read-write SLC1_TX_OVF_INT_ENA1 11 1 read-write SLC1_TOKEN0_1TO0_INT_ENA1 12 1 read-write SLC1_TOKEN1_1TO0_INT_ENA1 13 1 read-write SLC1_TX_DONE_INT_ENA1 14 1 read-write SLC1_TX_SUC_EOF_INT_ENA1 15 1 read-write SLC1_RX_DONE_INT_ENA1 16 1 read-write SLC1_RX_EOF_INT_ENA1 17 1 read-write SLC1_TOHOST_INT_ENA1 18 1 read-write SLC1_TX_DSCR_ERR_INT_ENA1 19 1 read-write SLC1_RX_DSCR_ERR_INT_ENA1 20 1 read-write SLC1_TX_DSCR_EMPTY_INT_ENA1 21 1 read-write SLC1_HOST_RD_ACK_INT_ENA1 22 1 read-write SLC1_WR_RETRY_DONE_INT_ENA1 23 1 read-write SLC1_TX_ERR_EOF_INT_ENA1 24 1 read-write DATE 0x1F8 0x20 0x16022500 DATE 0 32 read-write ID 0x1FC 0x20 0x00000100 ID 0 32 read-write SLCHOST Peripheral SLCHOST SLCHOST 0x3FF55000 0x0 0x104 registers HOST_SLCHOST_FUNC2_0 0x10 0x20 HOST_SLC_FUNC2_INT 24 1 read-write HOST_SLCHOST_FUNC2_1 0x14 0x20 HOST_SLC_FUNC2_INT_EN 0 1 read-write HOST_SLCHOST_FUNC2_2 0x20 0x20 0x00000001 HOST_SLC_FUNC1_MDSTAT 0 1 read-write HOST_SLCHOST_GPIO_STATUS0 0x34 0x20 HOST_GPIO_SDIO_INT0 0 32 read-only HOST_SLCHOST_GPIO_STATUS1 0x38 0x20 HOST_GPIO_SDIO_INT1 0 8 read-only HOST_SLCHOST_GPIO_IN0 0x3C 0x20 HOST_GPIO_SDIO_IN0 0 32 read-only HOST_SLCHOST_GPIO_IN1 0x40 0x20 HOST_GPIO_SDIO_IN1 0 8 read-only HOST_SLC0HOST_TOKEN_RDATA 0x44 0x20 HOST_SLC0_TOKEN0 0 12 read-only HOST_SLC0_RX_PF_VALID 12 1 read-only HOST_HOSTSLC0_TOKEN1 16 12 read-only HOST_SLC0_RX_PF_EOF 28 4 read-only HOST_SLC0_HOST_PF 0x48 0x20 HOST_SLC0_PF_DATA 0 32 read-only HOST_SLC1_HOST_PF 0x4C 0x20 HOST_SLC1_PF_DATA 0 32 read-only HOST_SLC0HOST_INT_RAW 0x50 0x20 HOST_SLC0_TOHOST_BIT0_INT_RAW 0 1 read-only HOST_SLC0_TOHOST_BIT1_INT_RAW 1 1 read-only HOST_SLC0_TOHOST_BIT2_INT_RAW 2 1 read-only HOST_SLC0_TOHOST_BIT3_INT_RAW 3 1 read-only HOST_SLC0_TOHOST_BIT4_INT_RAW 4 1 read-only HOST_SLC0_TOHOST_BIT5_INT_RAW 5 1 read-only HOST_SLC0_TOHOST_BIT6_INT_RAW 6 1 read-only HOST_SLC0_TOHOST_BIT7_INT_RAW 7 1 read-only HOST_SLC0_TOKEN0_1TO0_INT_RAW 8 1 read-only HOST_SLC0_TOKEN1_1TO0_INT_RAW 9 1 read-only HOST_SLC0_TOKEN0_0TO1_INT_RAW 10 1 read-only HOST_SLC0_TOKEN1_0TO1_INT_RAW 11 1 read-only HOST_SLC0HOST_RX_SOF_INT_RAW 12 1 read-only HOST_SLC0HOST_RX_EOF_INT_RAW 13 1 read-only HOST_SLC0HOST_RX_START_INT_RAW 14 1 read-only HOST_SLC0HOST_TX_START_INT_RAW 15 1 read-only HOST_SLC0_RX_UDF_INT_RAW 16 1 read-only HOST_SLC0_TX_OVF_INT_RAW 17 1 read-only HOST_SLC0_RX_PF_VALID_INT_RAW 18 1 read-only HOST_SLC0_EXT_BIT0_INT_RAW 19 1 read-only HOST_SLC0_EXT_BIT1_INT_RAW 20 1 read-only HOST_SLC0_EXT_BIT2_INT_RAW 21 1 read-only HOST_SLC0_EXT_BIT3_INT_RAW 22 1 read-only HOST_SLC0_RX_NEW_PACKET_INT_RAW 23 1 read-only HOST_SLC0_HOST_RD_RETRY_INT_RAW 24 1 read-only HOST_GPIO_SDIO_INT_RAW 25 1 read-only HOST_SLC1HOST_INT_RAW 0x54 0x20 HOST_SLC1_TOHOST_BIT0_INT_RAW 0 1 read-only HOST_SLC1_TOHOST_BIT1_INT_RAW 1 1 read-only HOST_SLC1_TOHOST_BIT2_INT_RAW 2 1 read-only HOST_SLC1_TOHOST_BIT3_INT_RAW 3 1 read-only HOST_SLC1_TOHOST_BIT4_INT_RAW 4 1 read-only HOST_SLC1_TOHOST_BIT5_INT_RAW 5 1 read-only HOST_SLC1_TOHOST_BIT6_INT_RAW 6 1 read-only HOST_SLC1_TOHOST_BIT7_INT_RAW 7 1 read-only HOST_SLC1_TOKEN0_1TO0_INT_RAW 8 1 read-only HOST_SLC1_TOKEN1_1TO0_INT_RAW 9 1 read-only HOST_SLC1_TOKEN0_0TO1_INT_RAW 10 1 read-only HOST_SLC1_TOKEN1_0TO1_INT_RAW 11 1 read-only HOST_SLC1HOST_RX_SOF_INT_RAW 12 1 read-only HOST_SLC1HOST_RX_EOF_INT_RAW 13 1 read-only HOST_SLC1HOST_RX_START_INT_RAW 14 1 read-only HOST_SLC1HOST_TX_START_INT_RAW 15 1 read-only HOST_SLC1_RX_UDF_INT_RAW 16 1 read-only HOST_SLC1_TX_OVF_INT_RAW 17 1 read-only HOST_SLC1_RX_PF_VALID_INT_RAW 18 1 read-only HOST_SLC1_EXT_BIT0_INT_RAW 19 1 read-only HOST_SLC1_EXT_BIT1_INT_RAW 20 1 read-only HOST_SLC1_EXT_BIT2_INT_RAW 21 1 read-only HOST_SLC1_EXT_BIT3_INT_RAW 22 1 read-only HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW 23 1 read-only HOST_SLC1_HOST_RD_RETRY_INT_RAW 24 1 read-only HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW 25 1 read-only HOST_SLC0HOST_INT_ST 0x58 0x20 HOST_SLC0_TOHOST_BIT0_INT_ST 0 1 read-only HOST_SLC0_TOHOST_BIT1_INT_ST 1 1 read-only HOST_SLC0_TOHOST_BIT2_INT_ST 2 1 read-only HOST_SLC0_TOHOST_BIT3_INT_ST 3 1 read-only HOST_SLC0_TOHOST_BIT4_INT_ST 4 1 read-only HOST_SLC0_TOHOST_BIT5_INT_ST 5 1 read-only HOST_SLC0_TOHOST_BIT6_INT_ST 6 1 read-only HOST_SLC0_TOHOST_BIT7_INT_ST 7 1 read-only HOST_SLC0_TOKEN0_1TO0_INT_ST 8 1 read-only HOST_SLC0_TOKEN1_1TO0_INT_ST 9 1 read-only HOST_SLC0_TOKEN0_0TO1_INT_ST 10 1 read-only HOST_SLC0_TOKEN1_0TO1_INT_ST 11 1 read-only HOST_SLC0HOST_RX_SOF_INT_ST 12 1 read-only HOST_SLC0HOST_RX_EOF_INT_ST 13 1 read-only HOST_SLC0HOST_RX_START_INT_ST 14 1 read-only HOST_SLC0HOST_TX_START_INT_ST 15 1 read-only HOST_SLC0_RX_UDF_INT_ST 16 1 read-only HOST_SLC0_TX_OVF_INT_ST 17 1 read-only HOST_SLC0_RX_PF_VALID_INT_ST 18 1 read-only HOST_SLC0_EXT_BIT0_INT_ST 19 1 read-only HOST_SLC0_EXT_BIT1_INT_ST 20 1 read-only HOST_SLC0_EXT_BIT2_INT_ST 21 1 read-only HOST_SLC0_EXT_BIT3_INT_ST 22 1 read-only HOST_SLC0_RX_NEW_PACKET_INT_ST 23 1 read-only HOST_SLC0_HOST_RD_RETRY_INT_ST 24 1 read-only HOST_GPIO_SDIO_INT_ST 25 1 read-only HOST_SLC1HOST_INT_ST 0x5C 0x20 HOST_SLC1_TOHOST_BIT0_INT_ST 0 1 read-only HOST_SLC1_TOHOST_BIT1_INT_ST 1 1 read-only HOST_SLC1_TOHOST_BIT2_INT_ST 2 1 read-only HOST_SLC1_TOHOST_BIT3_INT_ST 3 1 read-only HOST_SLC1_TOHOST_BIT4_INT_ST 4 1 read-only HOST_SLC1_TOHOST_BIT5_INT_ST 5 1 read-only HOST_SLC1_TOHOST_BIT6_INT_ST 6 1 read-only HOST_SLC1_TOHOST_BIT7_INT_ST 7 1 read-only HOST_SLC1_TOKEN0_1TO0_INT_ST 8 1 read-only HOST_SLC1_TOKEN1_1TO0_INT_ST 9 1 read-only HOST_SLC1_TOKEN0_0TO1_INT_ST 10 1 read-only HOST_SLC1_TOKEN1_0TO1_INT_ST 11 1 read-only HOST_SLC1HOST_RX_SOF_INT_ST 12 1 read-only HOST_SLC1HOST_RX_EOF_INT_ST 13 1 read-only HOST_SLC1HOST_RX_START_INT_ST 14 1 read-only HOST_SLC1HOST_TX_START_INT_ST 15 1 read-only HOST_SLC1_RX_UDF_INT_ST 16 1 read-only HOST_SLC1_TX_OVF_INT_ST 17 1 read-only HOST_SLC1_RX_PF_VALID_INT_ST 18 1 read-only HOST_SLC1_EXT_BIT0_INT_ST 19 1 read-only HOST_SLC1_EXT_BIT1_INT_ST 20 1 read-only HOST_SLC1_EXT_BIT2_INT_ST 21 1 read-only HOST_SLC1_EXT_BIT3_INT_ST 22 1 read-only HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST 23 1 read-only HOST_SLC1_HOST_RD_RETRY_INT_ST 24 1 read-only HOST_SLC1_BT_RX_NEW_PACKET_INT_ST 25 1 read-only HOST_SLCHOST_PKT_LEN 0x60 0x20 HOST_HOSTSLC0_LEN 0 20 read-only HOST_HOSTSLC0_LEN_CHECK 20 12 read-only HOST_SLCHOST_STATE_W0 0x64 0x20 HOST_SLCHOST_STATE0 0 8 read-only HOST_SLCHOST_STATE1 8 8 read-only HOST_SLCHOST_STATE2 16 8 read-only HOST_SLCHOST_STATE3 24 8 read-only HOST_SLCHOST_STATE_W1 0x68 0x20 HOST_SLCHOST_STATE4 0 8 read-only HOST_SLCHOST_STATE5 8 8 read-only HOST_SLCHOST_STATE6 16 8 read-only HOST_SLCHOST_STATE7 24 8 read-only HOST_SLCHOST_CONF_W0 0x6C 0x20 HOST_SLCHOST_CONF0 0 8 read-write HOST_SLCHOST_CONF1 8 8 read-write HOST_SLCHOST_CONF2 16 8 read-write HOST_SLCHOST_CONF3 24 8 read-write HOST_SLCHOST_CONF_W1 0x70 0x20 HOST_SLCHOST_CONF4 0 8 read-write HOST_SLCHOST_CONF5 8 8 read-write HOST_SLCHOST_CONF6 16 8 read-write HOST_SLCHOST_CONF7 24 8 read-write HOST_SLCHOST_CONF_W2 0x74 0x20 HOST_SLCHOST_CONF8 0 8 read-write HOST_SLCHOST_CONF9 8 8 read-write HOST_SLCHOST_CONF10 16 8 read-write HOST_SLCHOST_CONF11 24 8 read-write HOST_SLCHOST_CONF_W3 0x78 0x20 0x000000C0 HOST_SLCHOST_CONF12 0 8 read-write HOST_SLCHOST_CONF13 8 8 read-write HOST_SLCHOST_CONF14 16 8 read-write HOST_SLCHOST_CONF15 24 8 read-write HOST_SLCHOST_CONF_W4 0x7C 0x20 0x000001FF HOST_SLCHOST_CONF16 SLC timeout value 0 8 read-write HOST_SLCHOST_CONF17 SLC timeout enable 8 8 read-write HOST_SLCHOST_CONF18 16 8 read-write HOST_SLCHOST_CONF19 Interrupt to target CPU 24 8 read-write HOST_SLCHOST_CONF_W5 0x80 0x20 HOST_SLCHOST_CONF20 0 8 read-write HOST_SLCHOST_CONF21 8 8 read-write HOST_SLCHOST_CONF22 16 8 read-write HOST_SLCHOST_CONF23 24 8 read-write HOST_SLCHOST_WIN_CMD 0x84 0x20 HOST_SLCHOST_CONF_W6 0x88 0x20 HOST_SLCHOST_CONF24 0 8 read-write HOST_SLCHOST_CONF25 8 8 read-write HOST_SLCHOST_CONF26 16 8 read-write HOST_SLCHOST_CONF27 24 8 read-write HOST_SLCHOST_CONF_W7 0x8C 0x20 HOST_SLCHOST_CONF28 0 8 read-write HOST_SLCHOST_CONF29 8 8 read-write HOST_SLCHOST_CONF30 16 8 read-write HOST_SLCHOST_CONF31 24 8 read-write HOST_SLCHOST_PKT_LEN0 0x90 0x20 HOST_HOSTSLC0_LEN0 0 20 read-only HOST_SLCHOST_PKT_LEN1 0x94 0x20 HOST_HOSTSLC0_LEN1 0 20 read-only HOST_SLCHOST_PKT_LEN2 0x98 0x20 HOST_HOSTSLC0_LEN2 0 20 read-only HOST_SLCHOST_CONF_W8 0x9C 0x20 HOST_SLCHOST_CONF32 0 8 read-write HOST_SLCHOST_CONF33 8 8 read-write HOST_SLCHOST_CONF34 16 8 read-write HOST_SLCHOST_CONF35 24 8 read-write HOST_SLCHOST_CONF_W9 0xA0 0x20 HOST_SLCHOST_CONF36 0 8 read-write HOST_SLCHOST_CONF37 8 8 read-write HOST_SLCHOST_CONF38 16 8 read-write HOST_SLCHOST_CONF39 24 8 read-write HOST_SLCHOST_CONF_W10 0xA4 0x20 HOST_SLCHOST_CONF40 0 8 read-write HOST_SLCHOST_CONF41 8 8 read-write HOST_SLCHOST_CONF42 16 8 read-write HOST_SLCHOST_CONF43 24 8 read-write HOST_SLCHOST_CONF_W11 0xA8 0x20 HOST_SLCHOST_CONF44 0 8 read-write HOST_SLCHOST_CONF45 8 8 read-write HOST_SLCHOST_CONF46 16 8 read-write HOST_SLCHOST_CONF47 24 8 read-write HOST_SLCHOST_CONF_W12 0xAC 0x20 HOST_SLCHOST_CONF48 0 8 read-write HOST_SLCHOST_CONF49 8 8 read-write HOST_SLCHOST_CONF50 16 8 read-write HOST_SLCHOST_CONF51 24 8 read-write HOST_SLCHOST_CONF_W13 0xB0 0x20 HOST_SLCHOST_CONF52 0 8 read-write HOST_SLCHOST_CONF53 8 8 read-write HOST_SLCHOST_CONF54 16 8 read-write HOST_SLCHOST_CONF55 24 8 read-write HOST_SLCHOST_CONF_W14 0xB4 0x20 HOST_SLCHOST_CONF56 0 8 read-write HOST_SLCHOST_CONF57 8 8 read-write HOST_SLCHOST_CONF58 16 8 read-write HOST_SLCHOST_CONF59 24 8 read-write HOST_SLCHOST_CONF_W15 0xB8 0x20 HOST_SLCHOST_CONF60 0 8 read-write HOST_SLCHOST_CONF61 8 8 read-write HOST_SLCHOST_CONF62 16 8 read-write HOST_SLCHOST_CONF63 24 8 read-write HOST_SLCHOST_CHECK_SUM0 0xBC 0x20 HOST_SLCHOST_CHECK_SUM0 0 32 read-only HOST_SLCHOST_CHECK_SUM1 0xC0 0x20 HOST_SLCHOST_CHECK_SUM1 0 32 read-only HOST_SLC1HOST_TOKEN_RDATA 0xC4 0x20 HOST_SLC1_TOKEN0 0 12 read-only HOST_SLC1_RX_PF_VALID 12 1 read-only HOST_HOSTSLC1_TOKEN1 16 12 read-only HOST_SLC1_RX_PF_EOF 28 4 read-only HOST_SLC0HOST_TOKEN_WDATA 0xC8 0x20 HOST_SLC0HOST_TOKEN0_WD 0 12 read-write HOST_SLC0HOST_TOKEN1_WD 16 12 read-write HOST_SLC1HOST_TOKEN_WDATA 0xCC 0x20 HOST_SLC1HOST_TOKEN0_WD 0 12 read-write HOST_SLC1HOST_TOKEN1_WD 16 12 read-write HOST_SLCHOST_TOKEN_CON 0xD0 0x20 HOST_SLC0HOST_TOKEN0_DEC 0 1 write-only HOST_SLC0HOST_TOKEN1_DEC 1 1 write-only HOST_SLC0HOST_TOKEN0_WR 2 1 write-only HOST_SLC0HOST_TOKEN1_WR 3 1 write-only HOST_SLC1HOST_TOKEN0_DEC 4 1 write-only HOST_SLC1HOST_TOKEN1_DEC 5 1 write-only HOST_SLC1HOST_TOKEN0_WR 6 1 write-only HOST_SLC1HOST_TOKEN1_WR 7 1 write-only HOST_SLC0HOST_LEN_WR 8 1 write-only HOST_SLC0HOST_INT_CLR 0xD4 0x20 HOST_SLC0_TOHOST_BIT0_INT_CLR 0 1 write-only HOST_SLC0_TOHOST_BIT1_INT_CLR 1 1 write-only HOST_SLC0_TOHOST_BIT2_INT_CLR 2 1 write-only HOST_SLC0_TOHOST_BIT3_INT_CLR 3 1 write-only HOST_SLC0_TOHOST_BIT4_INT_CLR 4 1 write-only HOST_SLC0_TOHOST_BIT5_INT_CLR 5 1 write-only HOST_SLC0_TOHOST_BIT6_INT_CLR 6 1 write-only HOST_SLC0_TOHOST_BIT7_INT_CLR 7 1 write-only HOST_SLC0_TOKEN0_1TO0_INT_CLR 8 1 write-only HOST_SLC0_TOKEN1_1TO0_INT_CLR 9 1 write-only HOST_SLC0_TOKEN0_0TO1_INT_CLR 10 1 write-only HOST_SLC0_TOKEN1_0TO1_INT_CLR 11 1 write-only HOST_SLC0HOST_RX_SOF_INT_CLR 12 1 write-only HOST_SLC0HOST_RX_EOF_INT_CLR 13 1 write-only HOST_SLC0HOST_RX_START_INT_CLR 14 1 write-only HOST_SLC0HOST_TX_START_INT_CLR 15 1 write-only HOST_SLC0_RX_UDF_INT_CLR 16 1 write-only HOST_SLC0_TX_OVF_INT_CLR 17 1 write-only HOST_SLC0_RX_PF_VALID_INT_CLR 18 1 write-only HOST_SLC0_EXT_BIT0_INT_CLR 19 1 write-only HOST_SLC0_EXT_BIT1_INT_CLR 20 1 write-only HOST_SLC0_EXT_BIT2_INT_CLR 21 1 write-only HOST_SLC0_EXT_BIT3_INT_CLR 22 1 write-only HOST_SLC0_RX_NEW_PACKET_INT_CLR 23 1 write-only HOST_SLC0_HOST_RD_RETRY_INT_CLR 24 1 write-only HOST_GPIO_SDIO_INT_CLR 25 1 write-only HOST_SLC1HOST_INT_CLR 0xD8 0x20 HOST_SLC1_TOHOST_BIT0_INT_CLR 0 1 write-only HOST_SLC1_TOHOST_BIT1_INT_CLR 1 1 write-only HOST_SLC1_TOHOST_BIT2_INT_CLR 2 1 write-only HOST_SLC1_TOHOST_BIT3_INT_CLR 3 1 write-only HOST_SLC1_TOHOST_BIT4_INT_CLR 4 1 write-only HOST_SLC1_TOHOST_BIT5_INT_CLR 5 1 write-only HOST_SLC1_TOHOST_BIT6_INT_CLR 6 1 write-only HOST_SLC1_TOHOST_BIT7_INT_CLR 7 1 write-only HOST_SLC1_TOKEN0_1TO0_INT_CLR 8 1 write-only HOST_SLC1_TOKEN1_1TO0_INT_CLR 9 1 write-only HOST_SLC1_TOKEN0_0TO1_INT_CLR 10 1 write-only HOST_SLC1_TOKEN1_0TO1_INT_CLR 11 1 write-only HOST_SLC1HOST_RX_SOF_INT_CLR 12 1 write-only HOST_SLC1HOST_RX_EOF_INT_CLR 13 1 write-only HOST_SLC1HOST_RX_START_INT_CLR 14 1 write-only HOST_SLC1HOST_TX_START_INT_CLR 15 1 write-only HOST_SLC1_RX_UDF_INT_CLR 16 1 write-only HOST_SLC1_TX_OVF_INT_CLR 17 1 write-only HOST_SLC1_RX_PF_VALID_INT_CLR 18 1 write-only HOST_SLC1_EXT_BIT0_INT_CLR 19 1 write-only HOST_SLC1_EXT_BIT1_INT_CLR 20 1 write-only HOST_SLC1_EXT_BIT2_INT_CLR 21 1 write-only HOST_SLC1_EXT_BIT3_INT_CLR 22 1 write-only HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR 23 1 write-only HOST_SLC1_HOST_RD_RETRY_INT_CLR 24 1 write-only HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR 25 1 write-only HOST_SLC0HOST_FUNC1_INT_ENA 0xDC 0x20 HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA 0 1 read-write HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA 1 1 read-write HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA 2 1 read-write HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA 3 1 read-write HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA 4 1 read-write HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA 5 1 read-write HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA 6 1 read-write HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA 7 1 read-write HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA 8 1 read-write HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA 9 1 read-write HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA 10 1 read-write HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA 11 1 read-write HOST_FN1_SLC0HOST_RX_SOF_INT_ENA 12 1 read-write HOST_FN1_SLC0HOST_RX_EOF_INT_ENA 13 1 read-write HOST_FN1_SLC0HOST_RX_START_INT_ENA 14 1 read-write HOST_FN1_SLC0HOST_TX_START_INT_ENA 15 1 read-write HOST_FN1_SLC0_RX_UDF_INT_ENA 16 1 read-write HOST_FN1_SLC0_TX_OVF_INT_ENA 17 1 read-write HOST_FN1_SLC0_RX_PF_VALID_INT_ENA 18 1 read-write HOST_FN1_SLC0_EXT_BIT0_INT_ENA 19 1 read-write HOST_FN1_SLC0_EXT_BIT1_INT_ENA 20 1 read-write HOST_FN1_SLC0_EXT_BIT2_INT_ENA 21 1 read-write HOST_FN1_SLC0_EXT_BIT3_INT_ENA 22 1 read-write HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA 23 1 read-write HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA 24 1 read-write HOST_FN1_GPIO_SDIO_INT_ENA 25 1 read-write HOST_SLC1HOST_FUNC1_INT_ENA 0xE0 0x20 HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA 0 1 read-write HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA 1 1 read-write HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA 2 1 read-write HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA 3 1 read-write HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA 4 1 read-write HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA 5 1 read-write HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA 6 1 read-write HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA 7 1 read-write HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA 8 1 read-write HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA 9 1 read-write HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA 10 1 read-write HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA 11 1 read-write HOST_FN1_SLC1HOST_RX_SOF_INT_ENA 12 1 read-write HOST_FN1_SLC1HOST_RX_EOF_INT_ENA 13 1 read-write HOST_FN1_SLC1HOST_RX_START_INT_ENA 14 1 read-write HOST_FN1_SLC1HOST_TX_START_INT_ENA 15 1 read-write HOST_FN1_SLC1_RX_UDF_INT_ENA 16 1 read-write HOST_FN1_SLC1_TX_OVF_INT_ENA 17 1 read-write HOST_FN1_SLC1_RX_PF_VALID_INT_ENA 18 1 read-write HOST_FN1_SLC1_EXT_BIT0_INT_ENA 19 1 read-write HOST_FN1_SLC1_EXT_BIT1_INT_ENA 20 1 read-write HOST_FN1_SLC1_EXT_BIT2_INT_ENA 21 1 read-write HOST_FN1_SLC1_EXT_BIT3_INT_ENA 22 1 read-write HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA 23 1 read-write HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA 24 1 read-write HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA 25 1 read-write HOST_SLC0HOST_FUNC2_INT_ENA 0xE4 0x20 HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA 0 1 read-write HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA 1 1 read-write HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA 2 1 read-write HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA 3 1 read-write HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA 4 1 read-write HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA 5 1 read-write HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA 6 1 read-write HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA 7 1 read-write HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA 8 1 read-write HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA 9 1 read-write HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA 10 1 read-write HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA 11 1 read-write HOST_FN2_SLC0HOST_RX_SOF_INT_ENA 12 1 read-write HOST_FN2_SLC0HOST_RX_EOF_INT_ENA 13 1 read-write HOST_FN2_SLC0HOST_RX_START_INT_ENA 14 1 read-write HOST_FN2_SLC0HOST_TX_START_INT_ENA 15 1 read-write HOST_FN2_SLC0_RX_UDF_INT_ENA 16 1 read-write HOST_FN2_SLC0_TX_OVF_INT_ENA 17 1 read-write HOST_FN2_SLC0_RX_PF_VALID_INT_ENA 18 1 read-write HOST_FN2_SLC0_EXT_BIT0_INT_ENA 19 1 read-write HOST_FN2_SLC0_EXT_BIT1_INT_ENA 20 1 read-write HOST_FN2_SLC0_EXT_BIT2_INT_ENA 21 1 read-write HOST_FN2_SLC0_EXT_BIT3_INT_ENA 22 1 read-write HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA 23 1 read-write HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA 24 1 read-write HOST_FN2_GPIO_SDIO_INT_ENA 25 1 read-write HOST_SLC1HOST_FUNC2_INT_ENA 0xE8 0x20 HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA 0 1 read-write HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA 1 1 read-write HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA 2 1 read-write HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA 3 1 read-write HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA 4 1 read-write HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA 5 1 read-write HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA 6 1 read-write HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA 7 1 read-write HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA 8 1 read-write HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA 9 1 read-write HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA 10 1 read-write HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA 11 1 read-write HOST_FN2_SLC1HOST_RX_SOF_INT_ENA 12 1 read-write HOST_FN2_SLC1HOST_RX_EOF_INT_ENA 13 1 read-write HOST_FN2_SLC1HOST_RX_START_INT_ENA 14 1 read-write HOST_FN2_SLC1HOST_TX_START_INT_ENA 15 1 read-write HOST_FN2_SLC1_RX_UDF_INT_ENA 16 1 read-write HOST_FN2_SLC1_TX_OVF_INT_ENA 17 1 read-write HOST_FN2_SLC1_RX_PF_VALID_INT_ENA 18 1 read-write HOST_FN2_SLC1_EXT_BIT0_INT_ENA 19 1 read-write HOST_FN2_SLC1_EXT_BIT1_INT_ENA 20 1 read-write HOST_FN2_SLC1_EXT_BIT2_INT_ENA 21 1 read-write HOST_FN2_SLC1_EXT_BIT3_INT_ENA 22 1 read-write HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA 23 1 read-write HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA 24 1 read-write HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA 25 1 read-write HOST_SLC0HOST_INT_ENA 0xEC 0x20 HOST_SLC0_TOHOST_BIT0_INT_ENA 0 1 read-write HOST_SLC0_TOHOST_BIT1_INT_ENA 1 1 read-write HOST_SLC0_TOHOST_BIT2_INT_ENA 2 1 read-write HOST_SLC0_TOHOST_BIT3_INT_ENA 3 1 read-write HOST_SLC0_TOHOST_BIT4_INT_ENA 4 1 read-write HOST_SLC0_TOHOST_BIT5_INT_ENA 5 1 read-write HOST_SLC0_TOHOST_BIT6_INT_ENA 6 1 read-write HOST_SLC0_TOHOST_BIT7_INT_ENA 7 1 read-write HOST_SLC0_TOKEN0_1TO0_INT_ENA 8 1 read-write HOST_SLC0_TOKEN1_1TO0_INT_ENA 9 1 read-write HOST_SLC0_TOKEN0_0TO1_INT_ENA 10 1 read-write HOST_SLC0_TOKEN1_0TO1_INT_ENA 11 1 read-write HOST_SLC0HOST_RX_SOF_INT_ENA 12 1 read-write HOST_SLC0HOST_RX_EOF_INT_ENA 13 1 read-write HOST_SLC0HOST_RX_START_INT_ENA 14 1 read-write HOST_SLC0HOST_TX_START_INT_ENA 15 1 read-write HOST_SLC0_RX_UDF_INT_ENA 16 1 read-write HOST_SLC0_TX_OVF_INT_ENA 17 1 read-write HOST_SLC0_RX_PF_VALID_INT_ENA 18 1 read-write HOST_SLC0_EXT_BIT0_INT_ENA 19 1 read-write HOST_SLC0_EXT_BIT1_INT_ENA 20 1 read-write HOST_SLC0_EXT_BIT2_INT_ENA 21 1 read-write HOST_SLC0_EXT_BIT3_INT_ENA 22 1 read-write HOST_SLC0_RX_NEW_PACKET_INT_ENA 23 1 read-write HOST_SLC0_HOST_RD_RETRY_INT_ENA 24 1 read-write HOST_GPIO_SDIO_INT_ENA 25 1 read-write HOST_SLC1HOST_INT_ENA 0xF0 0x20 HOST_SLC1_TOHOST_BIT0_INT_ENA 0 1 read-write HOST_SLC1_TOHOST_BIT1_INT_ENA 1 1 read-write HOST_SLC1_TOHOST_BIT2_INT_ENA 2 1 read-write HOST_SLC1_TOHOST_BIT3_INT_ENA 3 1 read-write HOST_SLC1_TOHOST_BIT4_INT_ENA 4 1 read-write HOST_SLC1_TOHOST_BIT5_INT_ENA 5 1 read-write HOST_SLC1_TOHOST_BIT6_INT_ENA 6 1 read-write HOST_SLC1_TOHOST_BIT7_INT_ENA 7 1 read-write HOST_SLC1_TOKEN0_1TO0_INT_ENA 8 1 read-write HOST_SLC1_TOKEN1_1TO0_INT_ENA 9 1 read-write HOST_SLC1_TOKEN0_0TO1_INT_ENA 10 1 read-write HOST_SLC1_TOKEN1_0TO1_INT_ENA 11 1 read-write HOST_SLC1HOST_RX_SOF_INT_ENA 12 1 read-write HOST_SLC1HOST_RX_EOF_INT_ENA 13 1 read-write HOST_SLC1HOST_RX_START_INT_ENA 14 1 read-write HOST_SLC1HOST_TX_START_INT_ENA 15 1 read-write HOST_SLC1_RX_UDF_INT_ENA 16 1 read-write HOST_SLC1_TX_OVF_INT_ENA 17 1 read-write HOST_SLC1_RX_PF_VALID_INT_ENA 18 1 read-write HOST_SLC1_EXT_BIT0_INT_ENA 19 1 read-write HOST_SLC1_EXT_BIT1_INT_ENA 20 1 read-write HOST_SLC1_EXT_BIT2_INT_ENA 21 1 read-write HOST_SLC1_EXT_BIT3_INT_ENA 22 1 read-write HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA 23 1 read-write HOST_SLC1_HOST_RD_RETRY_INT_ENA 24 1 read-write HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA 25 1 read-write HOST_SLC0HOST_RX_INFOR 0xF4 0x20 HOST_SLC0HOST_RX_INFOR 0 20 read-write HOST_SLC1HOST_RX_INFOR 0xF8 0x20 HOST_SLC1HOST_RX_INFOR 0 20 read-write HOST_SLC0HOST_LEN_WD 0xFC 0x20 HOST_SLC0HOST_LEN_WD 0 32 read-write HOST_SLC_APBWIN_WDATA 0x100 0x20 HOST_SLC_APBWIN_WDATA 0 32 read-write HOST_SLC_APBWIN_CONF 0x104 0x20 HOST_SLC_APBWIN_ADDR 0 28 read-write HOST_SLC_APBWIN_WR 28 1 read-write HOST_SLC_APBWIN_START 29 1 read-write HOST_SLC_APBWIN_RDATA 0x108 0x20 HOST_SLC_APBWIN_RDATA 0 32 read-only HOST_SLCHOST_RDCLR0 0x10C 0x20 0x0003C044 HOST_SLCHOST_SLC0_BIT7_CLRADDR 0 9 read-write HOST_SLCHOST_SLC0_BIT6_CLRADDR 9 9 read-write HOST_SLCHOST_RDCLR1 0x110 0x20 0x0003C1E0 HOST_SLCHOST_SLC1_BIT7_CLRADDR 0 9 read-write HOST_SLCHOST_SLC1_BIT6_CLRADDR 9 9 read-write HOST_SLC0HOST_INT_ENA1 0x114 0x20 HOST_SLC0_TOHOST_BIT0_INT_ENA1 0 1 read-write HOST_SLC0_TOHOST_BIT1_INT_ENA1 1 1 read-write HOST_SLC0_TOHOST_BIT2_INT_ENA1 2 1 read-write HOST_SLC0_TOHOST_BIT3_INT_ENA1 3 1 read-write HOST_SLC0_TOHOST_BIT4_INT_ENA1 4 1 read-write HOST_SLC0_TOHOST_BIT5_INT_ENA1 5 1 read-write HOST_SLC0_TOHOST_BIT6_INT_ENA1 6 1 read-write HOST_SLC0_TOHOST_BIT7_INT_ENA1 7 1 read-write HOST_SLC0_TOKEN0_1TO0_INT_ENA1 8 1 read-write HOST_SLC0_TOKEN1_1TO0_INT_ENA1 9 1 read-write HOST_SLC0_TOKEN0_0TO1_INT_ENA1 10 1 read-write HOST_SLC0_TOKEN1_0TO1_INT_ENA1 11 1 read-write HOST_SLC0HOST_RX_SOF_INT_ENA1 12 1 read-write HOST_SLC0HOST_RX_EOF_INT_ENA1 13 1 read-write HOST_SLC0HOST_RX_START_INT_ENA1 14 1 read-write HOST_SLC0HOST_TX_START_INT_ENA1 15 1 read-write HOST_SLC0_RX_UDF_INT_ENA1 16 1 read-write HOST_SLC0_TX_OVF_INT_ENA1 17 1 read-write HOST_SLC0_RX_PF_VALID_INT_ENA1 18 1 read-write HOST_SLC0_EXT_BIT0_INT_ENA1 19 1 read-write HOST_SLC0_EXT_BIT1_INT_ENA1 20 1 read-write HOST_SLC0_EXT_BIT2_INT_ENA1 21 1 read-write HOST_SLC0_EXT_BIT3_INT_ENA1 22 1 read-write HOST_SLC0_RX_NEW_PACKET_INT_ENA1 23 1 read-write HOST_SLC0_HOST_RD_RETRY_INT_ENA1 24 1 read-write HOST_GPIO_SDIO_INT_ENA1 25 1 read-write HOST_SLC1HOST_INT_ENA1 0x118 0x20 HOST_SLC1_TOHOST_BIT0_INT_ENA1 0 1 read-write HOST_SLC1_TOHOST_BIT1_INT_ENA1 1 1 read-write HOST_SLC1_TOHOST_BIT2_INT_ENA1 2 1 read-write HOST_SLC1_TOHOST_BIT3_INT_ENA1 3 1 read-write HOST_SLC1_TOHOST_BIT4_INT_ENA1 4 1 read-write HOST_SLC1_TOHOST_BIT5_INT_ENA1 5 1 read-write HOST_SLC1_TOHOST_BIT6_INT_ENA1 6 1 read-write HOST_SLC1_TOHOST_BIT7_INT_ENA1 7 1 read-write HOST_SLC1_TOKEN0_1TO0_INT_ENA1 8 1 read-write HOST_SLC1_TOKEN1_1TO0_INT_ENA1 9 1 read-write HOST_SLC1_TOKEN0_0TO1_INT_ENA1 10 1 read-write HOST_SLC1_TOKEN1_0TO1_INT_ENA1 11 1 read-write HOST_SLC1HOST_RX_SOF_INT_ENA1 12 1 read-write HOST_SLC1HOST_RX_EOF_INT_ENA1 13 1 read-write HOST_SLC1HOST_RX_START_INT_ENA1 14 1 read-write HOST_SLC1HOST_TX_START_INT_ENA1 15 1 read-write HOST_SLC1_RX_UDF_INT_ENA1 16 1 read-write HOST_SLC1_TX_OVF_INT_ENA1 17 1 read-write HOST_SLC1_RX_PF_VALID_INT_ENA1 18 1 read-write HOST_SLC1_EXT_BIT0_INT_ENA1 19 1 read-write HOST_SLC1_EXT_BIT1_INT_ENA1 20 1 read-write HOST_SLC1_EXT_BIT2_INT_ENA1 21 1 read-write HOST_SLC1_EXT_BIT3_INT_ENA1 22 1 read-write HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 23 1 read-write HOST_SLC1_HOST_RD_RETRY_INT_ENA1 24 1 read-write HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 25 1 read-write HOST_SLCHOSTDATE 0x178 0x20 0x16022500 HOST_SLCHOST_DATE 0 32 read-write HOST_SLCHOSTID 0x17C 0x20 0x00000600 HOST_SLCHOST_ID 0 32 read-write HOST_SLCHOST_CONF 0x1F0 0x20 HOST_FRC_SDIO11 0 5 read-write HOST_FRC_SDIO20 5 5 read-write HOST_FRC_NEG_SAMP 10 5 read-write HOST_FRC_POS_SAMP 15 5 read-write HOST_FRC_QUICK_IN 20 5 read-write HOST_SDIO20_INT_DELAY 25 1 read-write HOST_SDIO_PAD_PULLUP 26 1 read-write HOST_HSPEED_CON_EN 27 1 read-write HOST_SLCHOST_INF_ST 0x1F4 0x20 HOST_SDIO20_MODE 0 5 read-only HOST_SDIO_NEG_SAMP 5 5 read-only HOST_SDIO_QUICK_IN 10 5 read-only SPI0 SPI (Serial Peripheral Interface) Controller SPI 0x3FF43000 0x0 0x110 registers SPI0 28 CMD 0x0 0x20 FLASH_PER program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 16 1 read-write FLASH_PES program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 17 1 read-write USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 18 1 read-write FLASH_HPM Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. 19 1 read-write FLASH_RES This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. 20 1 read-write FLASH_DP Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 21 1 read-write FLASH_CE Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 22 1 read-write FLASH_BE Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 23 1 read-write FLASH_SE Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 24 1 read-write FLASH_PP Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. 25 1 read-write FLASH_WRSR Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 26 1 read-write FLASH_RDSR Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 27 1 read-write FLASH_RDID Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 28 1 read-write FLASH_WRDI Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 29 1 read-write FLASH_WREN Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 30 1 read-write FLASH_READ Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 31 1 read-write ADDR 0x4 0x20 CTRL 0x8 0x20 0x0020A400 FCS_CRC_EN For SPI1 initialize crc32 module before writing encrypted data to flash. Active low. 10 1 read-write TX_CRC_EN For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable 11 1 read-write WAIT_FLASH_IDLE_EN wait flash idle when program flash or erase flash. 1: enable 0: disable. 12 1 read-write FASTRD_MODE This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable. 13 1 read-write FREAD_DUAL In the read operations read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write RESANDRES The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable. 15 1 read-write FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write WP Write protect signal output when SPI is idle. 1: output high 0: output low. 21 1 read-write WRSR_2B two bytes data will be written to status register when it is set. 1: enable 0: disable. 22 1 read-write FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 read-write RD_BIT_ORDER In read-data (MISO) phase 1: LSB first 0: MSB first 25 1 read-write WR_BIT_ORDER In command address write-data (MOSI) phases 1: LSB firs 0: MSB first 26 1 read-write CTRL1 0xC 0x20 0x5FFF0000 CS_HOLD_DELAY_RES Delay cycles of resume Flash when resume Flash is enable by spi clock. 16 12 read-write CS_HOLD_DELAY SPI cs signal is delayed by spi clock cycles 28 4 read-write RD_STATUS 0x10 0x20 STATUS In the slave mode, it is the status for master to read out. 0 16 read-write WB_MODE Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit. 16 8 read-write STATUS_EXT In the slave mode,it is the status for master to read out. 24 8 read-write CTRL2 0x14 0x20 0x00000011 SETUP_TIME (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit. 0 4 read-write HOLD_TIME delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit. 4 4 read-write CK_OUT_LOW_MODE modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits. 8 4 read-write CK_OUT_HIGH_MODE modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits. 12 4 read-write MISO_DELAY_MODE MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle 16 2 read-write MISO_DELAY_NUM MISO signals are delayed by system clock cycles 18 3 read-write MOSI_DELAY_MODE MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle 21 2 read-write MOSI_DELAY_NUM MOSI signals are delayed by system clock cycles 23 3 read-write CS_DELAY_MODE spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle 26 2 read-write CS_DELAY_NUM spi_cs signal is delayed by system clock cycles 28 4 read-write CLOCK 0x18 0x20 0x80003043 CLKCNT_L In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. 0 6 read-write CLKCNT_H In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. 6 6 read-write CLKCNT_N In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) 12 6 read-write CLKDIV_PRE In the master mode it is pre-divider of spi_clk. 18 13 read-write CLK_EQU_SYSCLK In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. 31 1 read-write USER 0x1C 0x20 0x80000040 DOUTDIN Set the bit to enable full duplex communication. 1: enable 0: disable. 0 1 read-write CS_HOLD spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable. 4 1 read-write CS_SETUP spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable. 5 1 read-write CK_I_EDGE In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits. 6 1 read-write CK_OUT_EDGE the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. 7 1 read-write RD_BYTE_ORDER In read-data (MISO) phase 1: big-endian 0: little_endian 10 1 read-write WR_BYTE_ORDER In command address write-data (MOSI) phases 1: big-endian 0: litte_endian 11 1 read-write FWRITE_DUAL In the write operations read-data phase apply 2 signals 12 1 read-write FWRITE_QUAD In the write operations read-data phase apply 4 signals 13 1 read-write FWRITE_DIO In the write operations address phase and read-data phase apply 2 signals. 14 1 read-write FWRITE_QIO In the write operations address phase and read-data phase apply 4 signals. 15 1 read-write SIO Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. 16 1 read-write USR_HOLD_POL It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low 17 1 read-write USR_DOUT_HOLD spi is hold at data out state the bit combined with spi_usr_hold_pol bit. 18 1 read-write USR_DIN_HOLD spi is hold at data in state the bit combined with spi_usr_hold_pol bit. 19 1 read-write USR_DUMMY_HOLD spi is hold at dummy state the bit combined with spi_usr_hold_pol bit. 20 1 read-write USR_ADDR_HOLD spi is hold at address state the bit combined with spi_usr_hold_pol bit. 21 1 read-write USR_CMD_HOLD spi is hold at command state the bit combined with spi_usr_hold_pol bit. 22 1 read-write USR_PREP_HOLD spi is hold at prepare state the bit combined with spi_usr_hold_pol bit. 23 1 read-write USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. 24 1 read-write USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. 25 1 read-write USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. 26 1 read-write USR_MOSI This bit enable the write-data phase of an operation. 27 1 read-write USR_MISO This bit enable the read-data phase of an operation. 28 1 read-write USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write USR_ADDR This bit enable the address phase of an operation. 30 1 read-write USR_COMMAND This bit enable the command phase of an operation. 31 1 read-write USER1 0x20 0x20 0x5C000007 USR_DUMMY_CYCLELEN The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 8 read-write USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 read-only USER2 0x24 0x20 0x70000000 USR_COMMAND_VALUE The value of command. 0 16 read-write USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 read-write MOSI_DLEN 0x28 0x20 USR_MOSI_DBITLEN The length in bits of write-data. The register value shall be (bit_num-1). 0 24 read-write MISO_DLEN 0x2C 0x20 USR_MISO_DBITLEN The length in bits of read-data. The register value shall be (bit_num-1). 0 24 read-write SLV_WR_STATUS 0x30 0x20 SLV_WR_ST In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition. 0 32 read-write PIN 0x34 0x20 0x00000006 CS0_DIS SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin 0 1 read-write CS1_DIS SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin 1 1 read-write CS2_DIS SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin 2 1 read-write CK_DIS 1: spi clk out disable 0: spi clk out enable 5 1 read-write MASTER_CS_POL In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. 6 3 read-write MASTER_CK_SEL In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis. 11 3 read-write CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 29 1 read-write CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 30 1 read-write SLAVE 0x38 0x20 0x00000020 SLV_RD_BUF_DONE The interrupt raw bit for the completion of read-buffer operation in the slave mode. 0 1 read-write SLV_WR_BUF_DONE The interrupt raw bit for the completion of write-buffer operation in the slave mode. 1 1 read-write SLV_RD_STA_DONE The interrupt raw bit for the completion of read-status operation in the slave mode. 2 1 read-write SLV_WR_STA_DONE The interrupt raw bit for the completion of write-status operation in the slave mode. 3 1 read-write TRANS_DONE The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. 4 1 read-write INT_EN Interrupt enable bits for the below 5 sources 5 5 read-write CS_I_MODE In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter. 10 2 read-write SLV_LAST_COMMAND In the slave mode it is the value of command. 17 3 read-only SLV_LAST_STATE In the slave mode it is the state of spi state machine. 20 3 read-only TRANS_CNT The operations counter in both the master mode and the slave mode. 4: read-status 23 4 read-only SLV_CMD_DEFINE 1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer. 27 1 read-write SLV_WR_RD_STA_EN write and read status enable in the slave mode 28 1 read-write SLV_WR_RD_BUF_EN write and read buffer enable in the slave mode 29 1 read-write MODE 1: slave mode 0: master mode. 30 1 read-write SYNC_RESET Software reset enable, reset the spi clock line cs line and data lines. 31 1 read-write SLAVE1 0x3C 0x20 0x02000000 SLV_RDBUF_DUMMY_EN In the slave mode it is the enable bit of dummy phase for read-buffer operations. 0 1 read-write SLV_WRBUF_DUMMY_EN In the slave mode it is the enable bit of dummy phase for write-buffer operations. 1 1 read-write SLV_RDSTA_DUMMY_EN In the slave mode it is the enable bit of dummy phase for read-status operations. 2 1 read-write SLV_WRSTA_DUMMY_EN In the slave mode it is the enable bit of dummy phase for write-status operations. 3 1 read-write SLV_WR_ADDR_BITLEN In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1). 4 6 read-write SLV_RD_ADDR_BITLEN In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1). 10 6 read-write SLV_STATUS_READBACK In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS. 25 1 read-write SLV_STATUS_FAST_EN In the slave mode enable fast read status. 26 1 read-write SLV_STATUS_BITLEN In the slave mode it is the length of status bit. 27 5 read-write SLAVE2 0x40 0x20 SLV_RDSTA_DUMMY_CYCLELEN In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1). 0 8 read-write SLV_WRSTA_DUMMY_CYCLELEN In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1). 8 8 read-write SLV_RDBUF_DUMMY_CYCLELEN In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1). 16 8 read-write SLV_WRBUF_DUMMY_CYCLELEN In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1). 24 8 read-write SLAVE3 0x44 0x20 SLV_RDBUF_CMD_VALUE In the slave mode it is the value of read-buffer command. 0 8 read-write SLV_WRBUF_CMD_VALUE In the slave mode it is the value of write-buffer command. 8 8 read-write SLV_RDSTA_CMD_VALUE In the slave mode it is the value of read-status command. 16 8 read-write SLV_WRSTA_CMD_VALUE In the slave mode it is the value of write-status command. 24 8 read-write SLV_WRBUF_DLEN 0x48 0x20 SLV_WRBUF_DBITLEN In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1). 0 24 read-write SLV_RDBUF_DLEN 0x4C 0x20 SLV_RDBUF_DBITLEN In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1). 0 24 read-write CACHE_FCTRL 0x50 0x20 CACHE_REQ_EN For SPI0 Cache access enable 1: enable 0:disable. 0 1 read-write CACHE_USR_CMD_4BYTE For SPI0 cache read flash with 4 bytes command 1: enable 0:disable. 1 1 read-write CACHE_FLASH_USR_CMD For SPI0 cache read flash for user define command 1: enable 0:disable. 2 1 read-write CACHE_FLASH_PES_EN For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable. 3 1 read-write CACHE_SCTRL 0x54 0x20 0x15C04830 USR_SRAM_DIO For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable 1 1 read-write USR_SRAM_QIO For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable 2 1 read-write USR_WR_SRAM_DUMMY For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations. 3 1 read-write USR_RD_SRAM_DUMMY For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations. 4 1 read-write CACHE_SRAM_USR_RCMD For SPI0 In the spi sram mode cache read sram for user define command. 5 1 read-write SRAM_BYTES_LEN For SPI0 In the sram mode it is the byte length of spi read sram data. 6 8 read-write SRAM_DUMMY_CYCLELEN For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). 14 8 read-write SRAM_ADDR_BITLEN For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). 22 6 read-write CACHE_SRAM_USR_WCMD For SPI0 In the spi sram mode cache write sram for user define command 28 1 read-write SRAM_CMD 0x58 0x20 SRAM_DIO For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done. 0 1 read-write SRAM_QIO For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done. 1 1 read-write SRAM_RSTIO For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done 4 1 read-write SRAM_DRD_CMD 0x5C 0x20 CACHE_SRAM_USR_RD_CMD_VALUE For SPI0 When cache mode is enable it is the read command value of command phase for SRAM. 0 16 read-write CACHE_SRAM_USR_RD_CMD_BITLEN For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1). 28 4 read-write SRAM_DWR_CMD 0x60 0x20 CACHE_SRAM_USR_WR_CMD_VALUE For SPI0 When cache mode is enable it is the write command value of command phase for SRAM. 0 16 read-write CACHE_SRAM_USR_WR_CMD_BITLEN For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1). 28 4 read-write SLV_RD_BIT 0x64 0x20 SLV_RDATA_BIT In the slave mode it is the bit length of read data. The value is the length - 1. 0 24 read-write W0 0x80 0x20 BUF0 data buffer 0 32 read-write W1 0x84 0x20 BUF1 data buffer 0 32 read-write W2 0x88 0x20 BUF2 data buffer 0 32 read-write W3 0x8C 0x20 BUF3 data buffer 0 32 read-write W4 0x90 0x20 BUF4 data buffer 0 32 read-write W5 0x94 0x20 BUF5 data buffer 0 32 read-write W6 0x98 0x20 BUF6 data buffer 0 32 read-write W7 0x9C 0x20 BUF7 data buffer 0 32 read-write W8 0xA0 0x20 BUF8 data buffer 0 32 read-write W9 0xA4 0x20 BUF9 data buffer 0 32 read-write W10 0xA8 0x20 BUF10 data buffer 0 32 read-write W11 0xAC 0x20 BUF11 data buffer 0 32 read-write W12 0xB0 0x20 BUF12 data buffer 0 32 read-write W13 0xB4 0x20 BUF13 data buffer 0 32 read-write W14 0xB8 0x20 BUF14 data buffer 0 32 read-write W15 0xBC 0x20 BUF15 data buffer 0 32 read-write TX_CRC 0xC0 0x20 DATA For SPI1 the value of crc32 for 256 bits data. 0 32 read-write EXT0 0xF0 0x20 0x800A0050 T_PP_TIME page program delay time by system clock. 0 12 read-write T_PP_SHIFT page program delay time shift . 16 4 read-write T_PP_ENA page program delay enable. 31 1 read-write EXT1 0xF4 0x20 0x800F0000 T_ERASE_TIME erase flash delay time by system clock. 0 12 read-write T_ERASE_SHIFT erase flash delay time shift. 16 4 read-write T_ERASE_ENA erase flash delay enable. 31 1 read-write EXT2 0xF8 0x20 ST The status of spi state machine . 0 3 read-only EXT3 0xFC 0x20 INT_HOLD_ENA This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase. 0 2 read-write DMA_CONF 0x100 0x20 0x00000200 IN_RST The bit is used to reset in dma fsm and in data fifo pointer. 2 1 read-write OUT_RST The bit is used to reset out dma fsm and out data fifo pointer. 3 1 read-write AHBM_FIFO_RST reset spi dma ahb master fifo pointer. 4 1 read-write AHBM_RST reset spi dma ahb master. 5 1 read-write IN_LOOP_TEST Set bit to test in link. 6 1 read-write OUT_LOOP_TEST Set bit to test out link. 7 1 read-write OUT_AUTO_WRBACK when the link is empty jump to next automatically. 8 1 read-write OUT_EOF_MODE out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo. 9 1 read-write OUTDSCR_BURST_EN read descriptor use burst mode when read data for memory. 10 1 read-write INDSCR_BURST_EN read descriptor use burst mode when write data to memory. 11 1 read-write OUT_DATA_BURST_EN spi dma read data from memory in burst mode. 12 1 read-write DMA_RX_STOP spi dma read data stop when in continue tx/rx mode. 14 1 read-write DMA_TX_STOP spi dma write data stop when in continue tx/rx mode. 15 1 read-write DMA_CONTINUE spi dma continue tx/rx data. 16 1 read-write DMA_OUT_LINK 0x104 0x20 OUTLINK_ADDR The address of the first outlink descriptor. 0 20 read-write OUTLINK_STOP Set the bit to stop to use outlink descriptor. 28 1 read-write OUTLINK_START Set the bit to start to use outlink descriptor. 29 1 read-write OUTLINK_RESTART Set the bit to mount on new outlink descriptors. 30 1 read-write DMA_IN_LINK 0x108 0x20 INLINK_ADDR The address of the first inlink descriptor. 0 20 read-write INLINK_AUTO_RET when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong 20 1 read-write INLINK_STOP Set the bit to stop to use inlink descriptor. 28 1 read-write INLINK_START Set the bit to start to use inlink descriptor. 29 1 read-write INLINK_RESTART Set the bit to mount on new inlink descriptors. 30 1 read-write DMA_STATUS 0x10C 0x20 DMA_RX_EN spi dma read data status bit. 0 1 read-only DMA_TX_EN spi dma write data status bit. 1 1 read-only DMA_INT_ENA 0x110 0x20 INLINK_DSCR_EMPTY_INT_ENA The enable bit for lack of enough inlink descriptors. 0 1 read-write OUTLINK_DSCR_ERROR_INT_ENA The enable bit for outlink descriptor error. 1 1 read-write INLINK_DSCR_ERROR_INT_ENA The enable bit for inlink descriptor error. 2 1 read-write IN_DONE_INT_ENA The enable bit for completing usage of a inlink descriptor. 3 1 read-write IN_ERR_EOF_INT_ENA The enable bit for receiving error. 4 1 read-write IN_SUC_EOF_INT_ENA The enable bit for completing receiving all the packets from host. 5 1 read-write OUT_DONE_INT_ENA The enable bit for completing usage of a outlink descriptor . 6 1 read-write OUT_EOF_INT_ENA The enable bit for sending a packet to host done. 7 1 read-write OUT_TOTAL_EOF_INT_ENA The enable bit for sending all the packets to host done. 8 1 read-write DMA_INT_RAW 0x114 0x20 INLINK_DSCR_EMPTY_INT_RAW The raw bit for lack of enough inlink descriptors. 0 1 read-only OUTLINK_DSCR_ERROR_INT_RAW The raw bit for outlink descriptor error. 1 1 read-only INLINK_DSCR_ERROR_INT_RAW The raw bit for inlink descriptor error. 2 1 read-only IN_DONE_INT_RAW The raw bit for completing usage of a inlink descriptor. 3 1 read-only IN_ERR_EOF_INT_RAW The raw bit for receiving error. 4 1 read-only IN_SUC_EOF_INT_RAW The raw bit for completing receiving all the packets from host. 5 1 read-only OUT_DONE_INT_RAW The raw bit for completing usage of a outlink descriptor. 6 1 read-only OUT_EOF_INT_RAW The raw bit for sending a packet to host done. 7 1 read-only OUT_TOTAL_EOF_INT_RAW The raw bit for sending all the packets to host done. 8 1 read-only DMA_INT_ST 0x118 0x20 INLINK_DSCR_EMPTY_INT_ST The status bit for lack of enough inlink descriptors. 0 1 read-only OUTLINK_DSCR_ERROR_INT_ST The status bit for outlink descriptor error. 1 1 read-only INLINK_DSCR_ERROR_INT_ST The status bit for inlink descriptor error. 2 1 read-only IN_DONE_INT_ST The status bit for completing usage of a inlink descriptor. 3 1 read-only IN_ERR_EOF_INT_ST The status bit for receiving error. 4 1 read-only IN_SUC_EOF_INT_ST The status bit for completing receiving all the packets from host. 5 1 read-only OUT_DONE_INT_ST The status bit for completing usage of a outlink descriptor. 6 1 read-only OUT_EOF_INT_ST The status bit for sending a packet to host done. 7 1 read-only OUT_TOTAL_EOF_INT_ST The status bit for sending all the packets to host done. 8 1 read-only DMA_INT_CLR 0x11C 0x20 INLINK_DSCR_EMPTY_INT_CLR The clear bit for lack of enough inlink descriptors. 0 1 read-write OUTLINK_DSCR_ERROR_INT_CLR The clear bit for outlink descriptor error. 1 1 read-write INLINK_DSCR_ERROR_INT_CLR The clear bit for inlink descriptor error. 2 1 read-write IN_DONE_INT_CLR The clear bit for completing usage of a inlink descriptor. 3 1 read-write IN_ERR_EOF_INT_CLR The clear bit for receiving error. 4 1 read-write IN_SUC_EOF_INT_CLR The clear bit for completing receiving all the packets from host. 5 1 read-write OUT_DONE_INT_CLR The clear bit for completing usage of a outlink descriptor. 6 1 read-write OUT_EOF_INT_CLR The clear bit for sending a packet to host done. 7 1 read-write OUT_TOTAL_EOF_INT_CLR The clear bit for sending all the packets to host done. 8 1 read-write IN_ERR_EOF_DES_ADDR 0x120 0x20 DMA_IN_ERR_EOF_DES_ADDR The inlink descriptor address when spi dma produce receiving error. 0 32 read-only IN_SUC_EOF_DES_ADDR 0x124 0x20 DMA_IN_SUC_EOF_DES_ADDR The last inlink descriptor address when spi dma produce from_suc_eof. 0 32 read-only INLINK_DSCR 0x128 0x20 DMA_INLINK_DSCR The content of current in descriptor pointer. 0 32 read-only INLINK_DSCR_BF0 0x12C 0x20 DMA_INLINK_DSCR_BF0 The content of next in descriptor pointer. 0 32 read-only INLINK_DSCR_BF1 0x130 0x20 DMA_INLINK_DSCR_BF1 The content of current in descriptor data buffer pointer. 0 32 read-only OUT_EOF_BFR_DES_ADDR 0x134 0x20 DMA_OUT_EOF_BFR_DES_ADDR The address of buffer relative to the outlink descriptor that produce eof. 0 32 read-only OUT_EOF_DES_ADDR 0x138 0x20 DMA_OUT_EOF_DES_ADDR The last outlink descriptor address when spi dma produce to_eof. 0 32 read-only OUTLINK_DSCR 0x13C 0x20 DMA_OUTLINK_DSCR The content of current out descriptor pointer. 0 32 read-only OUTLINK_DSCR_BF0 0x140 0x20 DMA_OUTLINK_DSCR_BF0 The content of next out descriptor pointer. 0 32 read-only OUTLINK_DSCR_BF1 0x144 0x20 DMA_OUTLINK_DSCR_BF1 The content of current out descriptor data buffer pointer. 0 32 read-only DMA_RSTATUS 0x148 0x20 DMA_OUT_STATUS spi dma read data from memory status. 0 32 read-only DMA_TSTATUS 0x14C 0x20 DMA_IN_STATUS spi dma write data to memory status. 0 32 read-only DATE 0x3FC 0x20 0x01604270 DATE SPI register version. 0 28 read-only SPI1 SPI (Serial Peripheral Interface) Controller 0x3FF42000 SPI1 29 SPI1_DMA 52 SPI2 SPI (Serial Peripheral Interface) Controller 0x3FF64000 SPI2 30 SPI2_DMA 53 SPI3 SPI (Serial Peripheral Interface) Controller 0x3FF65000 SPI3 31 SPI3_DMA 54 TIMG0 Timer Group TIMG 0x3FF5F000 0x0 0xB0 registers TG0_T0_LEVEL 14 TG0_T1_LEVEL 15 TG0_WDT_LEVEL 16 TG0_LACT_LEVEL 17 TG0_T0_EDGE 58 TG0_T1_EDGE 59 TG0_WDT_EDGE 60 TG0_LACT_EDGE 61 T0CONFIG 0x0 0x20 0x60002000 ALARM_EN When set alarm is enabled 10 1 read-write LEVEL_INT_EN When set level type interrupt will be generated during alarm 11 1 read-write EDGE_INT_EN When set edge type interrupt will be generated during alarm 12 1 read-write DIVIDER Timer 0 clock (T0_clk) prescale value. 13 16 read-write AUTORELOAD When set timer 0 auto-reload at alarming is enabled 29 1 read-write INCREASE When set timer 0 time-base counter increment. When cleared timer 0 time-base counter decrement. 30 1 read-write EN When set timer 0 time-base counter is enabled 31 1 read-write T0LO 0x4 0x20 LO Register to store timer 0 time-base counter current value lower 32 bits. 0 32 read-only T0HI 0x8 0x20 HI Register to store timer 0 time-base counter current value higher 32 bits. 0 32 read-only T0UPDATE 0xC 0x20 UPDATE Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above) 0 32 write-only T0ALARMLO 0x10 0x20 ALARM_LO Timer 0 time-base counter value lower 32 bits that will trigger the alarm 0 32 read-write T0ALARMHI 0x14 0x20 ALARM_HI Timer 0 time-base counter value higher 32 bits that will trigger the alarm 0 32 read-write T0LOADLO 0x18 0x20 LOAD_LO Lower 32 bits of the value that will load into timer 0 time-base counter 0 32 read-write T0LOADHI 0x1C 0x20 LOAD_HI higher 32 bits of the value that will load into timer 0 time-base counter 0 32 read-write T0LOAD 0x20 0x20 LOAD Write any value will trigger timer 0 time-base counter reload 0 32 write-only T1CONFIG 0x24 0x20 0x60002000 ALARM_EN When set alarm is enabled 10 1 read-write LEVEL_INT_EN When set level type interrupt will be generated during alarm 11 1 read-write EDGE_INT_EN When set edge type interrupt will be generated during alarm 12 1 read-write DIVIDER Timer 1 clock (T1_clk) prescale value. 13 16 read-write AUTORELOAD When set timer 1 auto-reload at alarming is enabled 29 1 read-write INCREASE When set timer 1 time-base counter increment. When cleared timer 1 time-base counter decrement. 30 1 read-write EN When set timer 1 time-base counter is enabled 31 1 read-write T1LO 0x28 0x20 LO Register to store timer 1 time-base counter current value lower 32 bits. 0 32 read-only T1HI 0x2C 0x20 HI Register to store timer 1 time-base counter current value higher 32 bits. 0 32 read-only T1UPDATE 0x30 0x20 UPDATE Write any value will trigger a timer 1 time-base counter value update (timer 1 current value will be stored in registers above) 0 32 write-only T1ALARMLO 0x34 0x20 ALARM_LO Timer 1 time-base counter value lower 32 bits that will trigger the alarm 0 32 read-write T1ALARMHI 0x38 0x20 ALARM_HI Timer 1 time-base counter value higher 32 bits that will trigger the alarm 0 32 read-write T1LOADLO 0x3C 0x20 LOAD_LO Lower 32 bits of the value that will load into timer 1 time-base counter 0 32 read-write T1LOADHI 0x40 0x20 LOAD_HI higher 32 bits of the value that will load into timer 1 time-base counter 0 32 read-write T1LOAD 0x44 0x20 LOAD Write any value will trigger timer 1 time-base counter reload 0 32 write-only WDTCONFIG0 0x48 0x20 0x0004C000 WDT_FLASHBOOT_MOD_EN When set flash boot protection is enabled 14 1 read-write WDT_SYS_RESET_LENGTH length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us 15 3 read-write WDT_SYS_RESET_LENGTH read-write NS100 100ns 0 NS200 200ns 1 NS300 300ns 2 NS400 400ns 3 NS500 500ns 4 NS800 800ns 5 NS1600 1.6us 6 NS3200 3.2us 7 WDT_CPU_RESET_LENGTH length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us 18 3 read-write WDT_CPU_RESET_LENGTH read-write NS100 100ns 0 NS200 200ns 1 NS300 300ns 2 NS400 400ns 3 NS500 500ns 4 NS800 800ns 5 NS1600 1.6us 6 NS3200 3.2us 7 WDT_LEVEL_INT_EN When set level type interrupt generation is enabled 21 1 read-write WDT_EDGE_INT_EN When set edge type interrupt generation is enabled 22 1 read-write WDT_STG3 Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system 23 2 read-write WDT_STG3 read-write OFF Off 0 INTERRUPT Interrupt 1 RESET Reset CPU 2 RESET_SYS Reset system 3 WDT_STG2 Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system 25 2 read-write WDT_STG1 Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system 27 2 read-write WDT_STG0 Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system 29 2 read-write WDT_EN When set SWDT is enabled 31 1 read-write WDTCONFIG1 0x4C 0x20 0x00010000 WDT_CLK_PRESCALE SWDT clock prescale value. Period = 12.5ns * value stored in this register 16 16 read-write WDTCONFIG2 0x50 0x20 0x018CBA80 WDT_STG0_HOLD Stage 0 timeout value in SWDT clock cycles 0 32 read-write WDTCONFIG3 0x54 0x20 0x07FFFFFF WDT_STG1_HOLD Stage 1 timeout value in SWDT clock cycles 0 32 read-write WDTCONFIG4 0x58 0x20 0x000FFFFF WDT_STG2_HOLD Stage 2 timeout value in SWDT clock cycles 0 32 read-write WDTCONFIG5 0x5C 0x20 0x000FFFFF WDT_STG3_HOLD Stage 3 timeout value in SWDT clock cycles 0 32 read-write WDTFEED 0x60 0x20 WDT_FEED Write any value will feed SWDT 0 32 write-only WDTWPROTECT 0x64 0x20 0x50D83AA1 WDT_WKEY If change its value from default then write protection is on. 0 32 read-write RTCCALICFG 0x68 0x20 0x00013000 RTC_CALI_START_CYCLING 12 1 read-write RTC_CALI_CLK_SEL 13 2 read-write RTC_CALI_RDY 15 1 read-only RTC_CALI_MAX 16 15 read-write RTC_CALI_START 31 1 read-write RTCCALICFG1 0x6C 0x20 RTC_CALI_VALUE 7 25 read-only LACTCONFIG 0x70 0x20 0x60002300 LACT_RTC_ONLY 7 1 read-write LACT_CPST_EN 8 1 read-write LACT_LAC_EN 9 1 read-write LACT_ALARM_EN 10 1 read-write LACT_LEVEL_INT_EN 11 1 read-write LACT_EDGE_INT_EN 12 1 read-write LACT_DIVIDER 13 16 read-write LACT_AUTORELOAD 29 1 read-write LACT_INCREASE 30 1 read-write LACT_EN 31 1 read-write LACTRTC 0x74 0x20 LACT_RTC_STEP_LEN 6 26 read-write LACTLO 0x78 0x20 LACT_LO 0 32 read-only LACTHI 0x7C 0x20 LACT_HI 0 32 read-only LACTUPDATE 0x80 0x20 LACT_UPDATE 0 32 write-only LACTALARMLO 0x84 0x20 LACT_ALARM_LO 0 32 read-write LACTALARMHI 0x88 0x20 LACT_ALARM_HI 0 32 read-write LACTLOADLO 0x8C 0x20 LACT_LOAD_LO 0 32 read-write LACTLOADHI 0x90 0x20 LACT_LOAD_HI 0 32 read-write LACTLOAD 0x94 0x20 LACT_LOAD 0 32 write-only INT_ENA_TIMERS 0x98 0x20 T0_INT_ENA interrupt when timer0 alarm 0 1 read-write T1_INT_ENA interrupt when timer1 alarm 1 1 read-write WDT_INT_ENA Interrupt when an interrupt stage timeout 2 1 read-write LACT_INT_ENA 3 1 read-write INT_RAW_TIMERS 0x9C 0x20 T0_INT_RAW interrupt when timer0 alarm 0 1 read-only T1_INT_RAW interrupt when timer1 alarm 1 1 read-only WDT_INT_RAW Interrupt when an interrupt stage timeout 2 1 read-only LACT_INT_RAW 3 1 read-only INT_ST_TIMERS 0xA0 0x20 T0_INT_ST interrupt when timer0 alarm 0 1 read-only T1_INT_ST interrupt when timer1 alarm 1 1 read-only WDT_INT_ST Interrupt when an interrupt stage timeout 2 1 read-only LACT_INT_ST 3 1 read-only INT_CLR_TIMERS 0xA4 0x20 T0_INT_CLR interrupt when timer0 alarm 0 1 write-only T1_INT_CLR interrupt when timer1 alarm 1 1 write-only WDT_INT_CLR Interrupt when an interrupt stage timeout 2 1 write-only LACT_INT_CLR 3 1 write-only NTIMERS_DATE 0xF8 0x20 0x01604290 NTIMERS_DATE Version of this regfile 0 28 read-write TIMGCLK 0xFC 0x20 CLK_EN Force clock enable for this regfile 31 1 read-write TIMG1 Timer Group 0x3FF60000 TG1_T0_LEVEL 18 TG1_T1_LEVEL 19 TG1_WDT_LEVEL 20 TG1_LACT_LEVEL 21 TG1_T0_EDGE 62 TG1_T1_EDGE 63 TG1_WDT_EDGE 64 TG1_LACT_EDGE 65 TWAI Two-Wire Automotive Interface TWAI 0x3FF6B000 0x0 0x6C registers TWAI 45 MODE Mode Register 0x0 0x20 0x00000001 RESET_MODE This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode. 0 1 read-write LISTEN_ONLY_MODE 1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter. 1 1 read-write SELF_TEST_MODE 1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command. 2 1 read-write RX_FILTER_MODE This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode. 3 1 read-write CMD Command Register 0x4 0x20 TX_REQ Set the bit to 1 to allow the driving nodes start transmission. 0 1 write-only ABORT_TX Set the bit to 1 to cancel a pending transmission request. 1 1 write-only RELEASE_BUF Set the bit to 1 to release the RX buffer. 2 1 write-only CLR_OVERRUN Set the bit to 1 to clear the data overrun status bit. 3 1 write-only SELF_RX_REQ Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. 4 1 write-only STATUS Status register 0x8 0x20 RX_BUF_ST 1: The data in the RX buffer is not empty, with at least one received data packet. 0 1 read-only OVERRUN_ST 1: The RX FIFO is full and data overrun has occurred. 1 1 read-only TX_BUF_ST 1: The TX buffer is empty, the CPU may write a message into it. 2 1 read-only TX_COMPLETE 1: The TWAI controller has successfully received a packet from the bus. 3 1 read-only RX_ST 1: The TWAI Controller is receiving a message from the bus. 4 1 read-only TX_ST 1: The TWAI Controller is transmitting a message to the bus. 5 1 read-only ERR_ST 1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG. 6 1 read-only BUS_OFF_ST 1: In bus-off status, the TWAI Controller is no longer involved in bus activities. 7 1 read-only MISS_ST This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete 8 1 read-only INT_RAW Interrupt Register 0xC 0x20 RX_INT_ST Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO. 0 1 read-only TX_INT_ST Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute. 1 1 read-only ERR_WARN_INT_ST Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0). 2 1 read-only OVERRUN_INT_ST Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO. 3 1 read-only ERR_PASSIVE_INT_ST Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters. 5 1 read-only ARB_LOST_INT_ST Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated. 6 1 read-only BUS_ERR_INT_ST Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus. 7 1 read-only INT_ENA Interrupt Enable Register 0x10 0x20 RX_INT_ENA Set this bit to 1 to enable receive interrupt. 0 1 read-write TX_INT_ENA Set this bit to 1 to enable transmit interrupt. 1 1 read-write ERR_WARN_INT_ENA Set this bit to 1 to enable error warning interrupt. 2 1 read-write OVERRUN_INT_ENA Set this bit to 1 to enable data overrun interrupt. 3 1 read-write ERR_PASSIVE_INT_ENA Set this bit to 1 to enable error passive interrupt. 5 1 read-write ARB_LOST_INT_ENA Set this bit to 1 to enable arbitration lost interrupt. 6 1 read-write BUS_ERR_INT_ENA Set this bit to 1 to enable error interrupt. 7 1 read-write BUS_TIMING_0 Bus Timing Register 0 0x18 0x20 BAUD_PRESC Baud Rate Prescaler, determines the frequency dividing ratio. 0 14 SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 BUS_TIMING_1 Bus Timing Register 1 0x1C 0x20 TIME_SEG1 The width of PBS1. 0 4 TIME_SEG2 The width of PBS2. 4 3 TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 ARB_LOST_CAP Arbitration Lost Capture Register 0x2C 0x20 ARB_LOST_CAP This register contains information about the bit position of lost arbitration. 0 5 read-only ERR_CODE_CAP Error Code Capture Register 0x30 0x20 ECC_SEGMENT This register contains information about the location of errors, see Table 181 for details. 0 5 read-only ECC_DIRECTION This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message 5 1 read-only ECC_TYPE This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error 6 2 read-only ERR_WARNING_LIMIT Error Warning Limit Register 0x34 0x20 0x00000060 ERR_WARNING_LIMIT Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 RX_ERR_CNT Receive Error Counter Register 0x38 0x20 RX_ERR_CNT The RX error counter register, reflects value changes under reception status. 0 8 TX_ERR_CNT Transmit Error Counter Register 0x3C 0x20 TX_ERR_CNT The TX error counter register, reflects value changes under transmission status. 0 8 DATA_0 Data register 0 0x40 0x20 TX_BYTE_0 In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_1 Data register 1 0x44 0x20 TX_BYTE_1 In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_2 Data register 2 0x48 0x20 TX_BYTE_2 In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_3 Data register 3 0x4C 0x20 TX_BYTE_3 In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_4 Data register 4 0x50 0x20 TX_BYTE_4 In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_5 Data register 5 0x54 0x20 TX_BYTE_5 In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_6 Data register 6 0x58 0x20 TX_BYTE_6 In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_7 Data register 7 0x5C 0x20 TX_BYTE_7 In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_8 Data register 8 0x60 0x20 TX_BYTE_8 Stored the 8th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_9 Data register 9 0x64 0x20 TX_BYTE_9 Stored the 9th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_10 Data register 10 0x68 0x20 TX_BYTE_10 Stored the 10th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_11 Data register 11 0x6C 0x20 TX_BYTE_11 Stored the 11th byte information of the data to be transmitted under operating mode. 0 8 write-only DATA_12 Data register 12 0x70 0x20 TX_BYTE_12 Stored the 12th byte information of the data to be transmitted under operating mode. 0 8 write-only RX_MESSAGE_CNT Receive Message Counter Register 0x74 0x20 RX_MESSAGE_COUNTER This register reflects the number of messages available within the RX FIFO. 0 7 read-only CLOCK_DIVIDER Clock Divider register 0x7C 0x20 CD These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. 0 8 read-write CLOCK_OFF This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 UART0 UART (Universal Asynchronous Receiver-Transmitter) Controller UART 0x3FF40000 0x0 0x7C registers UART0 34 FIFO 0x0 0x20 RXFIFO_RD_BYTE This register stores one byte data read by rx fifo. 0 8 read-write INT_RAW 0x4 0x20 RXFIFO_FULL_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd). 0 1 read-only TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) . 1 1 read-only PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects the parity error of data. 2 1 read-only FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects data's frame error . 3 1 read-only RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the fifo can store. 4 1 read-only DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal. 5 1 read-only CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal. 6 1 read-only BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit. 7 1 read-only RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 read-only SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1. 9 1 read-only SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1. 10 1 read-only GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the start bit. 11 1 read-only TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sendding 0 after all the datas in transmitter's fifo are send. 12 1 read-only TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send. 13 1 read-only TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send all the data in fifo. 14 1 read-only RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when rs485 detects the parity error. 15 1 read-only RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when rs485 detects the data frame error. 16 1 read-only RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver. 17 1 read-only AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars. 18 1 read-only INT_ST 0x8 0x20 RXFIFO_FULL_INT_ST This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 0 1 read-only TXFIFO_EMPTY_INT_ST This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. 1 1 read-only PARITY_ERR_INT_ST This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 2 1 read-only FRM_ERR_INT_ST This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1. 3 1 read-only RXFIFO_OVF_INT_ST This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 4 1 read-only DSR_CHG_INT_ST This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 5 1 read-only CTS_CHG_INT_ST This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 6 1 read-only BRK_DET_INT_ST This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 7 1 read-only RXFIFO_TOUT_INT_ST This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 8 1 read-only SW_XON_INT_ST This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 9 1 read-only SW_XOFF_INT_ST This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 10 1 read-only GLITCH_DET_INT_ST This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 11 1 read-only TX_BRK_DONE_INT_ST This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 12 1 read-only TX_BRK_IDLE_DONE_INT_ST This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. 13 1 read-only TX_DONE_INT_ST This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 14 1 read-only RS485_PARITY_ERR_INT_ST This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. 15 1 read-only RS485_FRM_ERR_INT_ST This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1. 16 1 read-only RS485_CLASH_INT_ST This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. 17 1 read-only AT_CMD_CHAR_DET_INT_ST This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. 18 1 read-only INT_ENA 0xC 0x20 RXFIFO_FULL_INT_ENA This is the enable bit for rxfifo_full_int_st register. 0 1 read-write TXFIFO_EMPTY_INT_ENA This is the enable bit for rxfifo_full_int_st register. 1 1 read-write PARITY_ERR_INT_ENA This is the enable bit for parity_err_int_st register. 2 1 read-write FRM_ERR_INT_ENA This is the enable bit for frm_err_int_st register. 3 1 read-write RXFIFO_OVF_INT_ENA This is the enable bit for rxfifo_ovf_int_st register. 4 1 read-write DSR_CHG_INT_ENA This is the enable bit for dsr_chg_int_st register. 5 1 read-write CTS_CHG_INT_ENA This is the enable bit for cts_chg_int_st register. 6 1 read-write BRK_DET_INT_ENA This is the enable bit for brk_det_int_st register. 7 1 read-write RXFIFO_TOUT_INT_ENA This is the enable bit for rxfifo_tout_int_st register. 8 1 read-write SW_XON_INT_ENA This is the enable bit for sw_xon_int_st register. 9 1 read-write SW_XOFF_INT_ENA This is the enable bit for sw_xoff_int_st register. 10 1 read-write GLITCH_DET_INT_ENA This is the enable bit for glitch_det_int_st register. 11 1 read-write TX_BRK_DONE_INT_ENA This is the enable bit for tx_brk_done_int_st register. 12 1 read-write TX_BRK_IDLE_DONE_INT_ENA This is the enable bit for tx_brk_idle_done_int_st register. 13 1 read-write TX_DONE_INT_ENA This is the enable bit for tx_done_int_st register. 14 1 read-write RS485_PARITY_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 15 1 read-write RS485_FRM_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 16 1 read-write RS485_CLASH_INT_ENA This is the enable bit for rs485_clash_int_st register. 17 1 read-write AT_CMD_CHAR_DET_INT_ENA This is the enable bit for at_cmd_char_det_int_st register. 18 1 read-write INT_CLR 0x10 0x20 RXFIFO_FULL_INT_CLR Set this bit to clear the rxfifo_full_int_raw interrupt. 0 1 write-only TXFIFO_EMPTY_INT_CLR Set this bit to clear txfifo_empty_int_raw interrupt. 1 1 write-only PARITY_ERR_INT_CLR Set this bit to clear parity_err_int_raw interrupt. 2 1 write-only FRM_ERR_INT_CLR Set this bit to clear frm_err_int_raw interrupt. 3 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear rxfifo_ovf_int_raw interrupt. 4 1 write-only DSR_CHG_INT_CLR Set this bit to clear the dsr_chg_int_raw interrupt. 5 1 write-only CTS_CHG_INT_CLR Set this bit to clear the cts_chg_int_raw interrupt. 6 1 write-only BRK_DET_INT_CLR Set this bit to clear the brk_det_int_raw interrupt. 7 1 write-only RXFIFO_TOUT_INT_CLR Set this bit to clear the rxfifo_tout_int_raw interrupt. 8 1 write-only SW_XON_INT_CLR Set this bit to clear the sw_xon_int_raw interrupt. 9 1 write-only SW_XOFF_INT_CLR Set this bit to clear the sw_xon_int_raw interrupt. 10 1 write-only GLITCH_DET_INT_CLR Set this bit to clear the glitch_det_int_raw interrupt. 11 1 write-only TX_BRK_DONE_INT_CLR Set this bit to clear the tx_brk_done_int_raw interrupt.. 12 1 write-only TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 13 1 write-only TX_DONE_INT_CLR Set this bit to clear the tx_done_int_raw interrupt. 14 1 write-only RS485_PARITY_ERR_INT_CLR Set this bit to clear the rs485_parity_err_int_raw interrupt. 15 1 write-only RS485_FRM_ERR_INT_CLR Set this bit to clear the rs485_frm_err_int_raw interrupt. 16 1 write-only RS485_CLASH_INT_CLR Set this bit to clear the rs485_clash_int_raw interrupt. 17 1 write-only AT_CMD_CHAR_DET_INT_CLR Set this bit to clear the at_cmd_char_det_int_raw interrupt. 18 1 write-only CLKDIV 0x14 0x20 0x000002B6 CLKDIV The register value is the integer part of the frequency divider's factor. 0 20 read-write FRAG The register value is the decimal part of the frequency divider's factor. 20 4 read-write AUTOBAUD 0x18 0x20 0x00001000 EN This is the enable bit for detecting baudrate. 0 1 read-write GLITCH_FILT when input pulse width is lower then this value igore this pulse.this register is used in autobaud detect process. 8 8 read-write STATUS 0x1C 0x20 RXFIFO_CNT (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits. 0 8 read-only ST_URX_OUT This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1 8 4 read-only DSRN This register stores the level value of the internal uart dsr signal. 13 1 read-only CTSN This register stores the level value of the internal uart cts signal. 14 1 read-only RXD This register stores the level value of the internal uart rxd signal. 15 1 read-only TXFIFO_CNT (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits. 16 8 read-only ST_UTX_OUT This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1 24 4 read-only DTRN The register represent the level value of the internal uart dsr signal. 29 1 read-only RTSN This register represent the level value of the internal uart cts signal. 30 1 read-only TXD This register represent the level value of the internal uart rxd signal. 31 1 read-only CONF0 0x20 0x20 0x0800001C PARITY This register is used to configure the parity check mode. 0:even 1:odd 0 1 read-write PARITY_EN Set this bit to enable uart parity check. 1 1 read-write BIT_NUM This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits 2 2 read-write STOP_BIT_NUM This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits 4 2 read-write SW_RTS This register is used to configure the software rts signal which is used in software flow control. 6 1 read-write SW_DTR This register is used to configure the software dtr signal which is used in software flow control.. 7 1 read-write TXD_BRK Set this bit to enbale transmitter to send 0 when the process of sending data is done. 8 1 read-write IRDA_DPLX Set this bit to enable irda loopback mode. 9 1 read-write IRDA_TX_EN This is the start enable bit for irda transmitter. 10 1 read-write IRDA_WCTL 1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0. 11 1 read-write IRDA_TX_INV Set this bit to inverse the level value of irda transmitter's level. 12 1 read-write IRDA_RX_INV Set this bit to inverse the level value of irda receiver's level. 13 1 read-write LOOPBACK Set this bit to enable uart loopback test mode. 14 1 read-write TX_FLOW_EN Set this bit to enable transmitter's flow control function. 15 1 read-write IRDA_EN Set this bit to enable irda protocol. 16 1 read-write RXFIFO_RST Set this bit to reset uart receiver's fifo. 17 1 read-write TXFIFO_RST Set this bit to reset uart transmitter's fifo. 18 1 read-write RXD_INV Set this bit to inverse the level value of uart rxd signal. 19 1 read-write CTS_INV Set this bit to inverse the level value of uart cts signal. 20 1 read-write DSR_INV Set this bit to inverse the level value of uart dsr signal. 21 1 read-write TXD_INV Set this bit to inverse the level value of uart txd signal. 22 1 read-write RTS_INV Set this bit to inverse the level value of uart rts signal. 23 1 read-write DTR_INV Set this bit to inverse the level value of uart dtr signal. 24 1 read-write CLK_EN 1.force clock on for registers.support clock only when write registers 25 1 read-write ERR_WR_MASK 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong. 26 1 read-write TICK_REF_ALWAYS_ON This register is used to select the clock.1.apb clock 0:ref_tick 27 1 read-write CONF1 0x24 0x20 0x00006060 RXFIFO_FULL_THRHD When receiver receives more data than its threshold value.receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd). 0 7 read-write TXFIFO_EMPTY_THRHD when the data amount in transmitter fifo is less than its threshold value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd) 8 7 read-write RX_FLOW_THRHD when receiver receives more data than its threshold value. receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd). 16 7 read-write RX_FLOW_EN This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal 23 1 read-write RX_TOUT_THRHD This register is used to configure the timeout value for uart receiver receiving a byte. 24 7 read-write RX_TOUT_EN This is the enble bit for uart receiver's timeout function. 31 1 read-write LOWPULSE 0x28 0x20 0x000FFFFF MIN_CNT This register stores the value of the minimum duration time for the low level pulse. it is used in baudrate-detect process. 0 20 read-only HIGHPULSE 0x2C 0x20 0x000FFFFF MIN_CNT This register stores the value of the maxinum duration time for the high level pulse. it is used in baudrate-detect process. 0 20 read-only RXD_CNT 0x30 0x20 RXD_EDGE_CNT This register stores the count of rxd edge change. it is used in baudrate-detect process. 0 10 read-only FLOW_CONF 0x34 0x20 SW_FLOW_CON_EN Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff . 0 1 read-write XONOFF_DEL Set this bit to remove flow control char from the received data. 1 1 read-write FORCE_XON Set this bit to clear ctsn to stop the transmitter from sending data. 2 1 read-write FORCE_XOFF Set this bit to set ctsn to enable the transmitter to go on sending data. 3 1 read-write SEND_XON Set this bit to send xon char. it is cleared by hardware automatically. 4 1 read-write SEND_XOFF Set this bit to send xoff char. it is cleared by hardware automatically. 5 1 read-write SLEEP_CONF 0x38 0x20 0x000000F0 ACTIVE_THRESHOLD When the input rxd edge changes more than this register value. the uart is active from light sleeping mode. 0 10 read-write SWFC_CONF 0x3C 0x20 0x1311E000 XON_THRESHOLD when the data amount in receiver's fifo is more than this register value. it will send a xoff char with uart_sw_flow_con_en set to 1. 0 8 read-write XOFF_THRESHOLD When the data amount in receiver's fifo is less than this register value. it will send a xon char with uart_sw_flow_con_en set to 1. 8 8 read-write XON_CHAR This register stores the xon flow control char. 16 8 read-write XOFF_CHAR This register stores the xoff flow control char. 24 8 read-write IDLE_CONF 0x40 0x20 0x00A40100 RX_IDLE_THRHD when receiver takes more time than this register value to receive a byte data. it will produce frame end signal for uhci to stop receiving data. 0 10 read-write TX_IDLE_NUM This register is used to configure the duration time between transfers. 10 10 read-write TX_BRK_NUM This register is used to configure the num of 0 send after the process of sending data is done. it is active when txd_brk is set to 1. 20 8 read-write RS485_CONF 0x44 0x20 RS485_EN Set this bit to choose rs485 mode. 0 1 read-write DL0_EN Set this bit to delay the stop bit by 1 bit. 1 1 read-write DL1_EN Set this bit to delay the stop bit by 1 bit. 2 1 read-write RS485TX_RX_EN Set this bit to enable loopback transmitter's output data signal to receiver's input data signal. 3 1 read-write RS485RXBY_TX_EN 1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy. 4 1 read-write RS485_RX_DLY_NUM This register is used to delay the receiver's internal data signal. 5 1 read-write RS485_TX_DLY_NUM This register is used to delay the transmitter's internal data signal. 6 4 read-write AT_CMD_PRECNT 0x48 0x20 0x00186A00 PRE_IDLE_NUM This register is used to configure the idle duration time before the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char. 0 24 read-write AT_CMD_POSTCNT 0x4C 0x20 0x00186A00 POST_IDLE_NUM This register is used to configure the duration time between the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char. 0 24 read-write AT_CMD_GAPTOUT 0x50 0x20 0x00001E00 RX_GAP_TOUT This register is used to configure the duration time between the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars. 0 24 read-write AT_CMD_CHAR 0x54 0x20 0x0000032B AT_CMD_CHAR This register is used to configure the content of at_cmd char. 0 8 read-write CHAR_NUM This register is used to configure the num of continous at_cmd chars received by receiver. 8 8 read-write MEM_CONF 0x58 0x20 0x00000088 MEM_PD Set this bit to power down mem.when reg_mem_pd registers in the 3 uarts are all set to 1 mem will enter low power mode. 0 1 read-write RX_SIZE This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128. 3 4 read-write TX_SIZE This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128. 7 4 read-write RX_FLOW_THRHD_H3 refer to the rx_flow_thrhd's describtion. 15 3 read-write RX_TOUT_THRHD_H3 refer to the rx_tout_thrhd's describtion. 18 3 read-write XON_THRESHOLD_H2 refer to the uart_xon_threshold's describtion. 21 2 read-write XOFF_THRESHOLD_H2 refer to the uart_xoff_threshold's describtion. 23 2 read-write RX_MEM_FULL_THRHD refer to the rxfifo_full_thrhd's describtion. 25 3 read-write TX_MEM_EMPTY_THRHD refer to txfifo_empty_thrhd 's describtion. 28 3 read-write MEM_TX_STATUS 0x5C 0x20 MEM_TX_STATUS 0 24 read-only MEM_RX_STATUS 0x60 0x20 MEM_RX_STATUS This register stores the current uart rx mem read address and rx mem write address 0 24 read-only MEM_RX_RD_ADDR This register stores the rx mem read address 2 11 read-only MEM_RX_WR_ADDR This register stores the rx mem write address 13 11 read-only MEM_CNT_STATUS 0x64 0x20 RX_MEM_CNT refer to the rxfifo_cnt's describtion. 0 3 read-only TX_MEM_CNT refer to the txfifo_cnt's describtion. 3 3 read-only POSPULSE 0x68 0x20 0x000FFFFF POSEDGE_MIN_CNT This register stores the count of rxd posedge edge. it is used in boudrate-detect process. 0 20 read-only NEGPULSE 0x6C 0x20 0x000FFFFF NEGEDGE_MIN_CNT This register stores the count of rxd negedge edge. it is used in boudrate-detect process. 0 20 read-only DATE 0x78 0x20 0x15122500 DATE 0 32 read-write ID 0x7C 0x20 0x00000500 ID 0 32 read-write UART1 UART (Universal Asynchronous Receiver-Transmitter) Controller 0x3FF50000 UART1 35 UART2 UART (Universal Asynchronous Receiver-Transmitter) Controller 0x3FF6E000 UART2 36 UHCI0 Universal Host Controller Interface UHCI 0x3FF54000 0x0 0xC8 registers UHCI0 12 CONF0 0x0 0x20 0x00370100 IN_RST Set this bit to reset in link operations. 0 1 read-write OUT_RST Set this bit to reset out link operations. 1 1 read-write AHBM_FIFO_RST Set this bit to reset dma ahb fifo. 2 1 read-write AHBM_RST Set this bit to reset dma ahb interface. 3 1 read-write IN_LOOP_TEST Set this bit to enable loop test for in links. 4 1 read-write OUT_LOOP_TEST Set this bit to enable loop test for out links. 5 1 read-write OUT_AUTO_WRBACK when in link's length is 0 go on to use the next in link automatically. 6 1 read-write OUT_NO_RESTART_CLR don't use 7 1 read-write OUT_EOF_MODE Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data 8 1 read-write UART0_CE Set this bit to use UART to transmit or receive data. 9 1 read-write UART1_CE Set this bit to use UART1 to transmit or receive data. 10 1 read-write UART2_CE Set this bit to use UART2 to transmit or receive data. 11 1 read-write OUTDSCR_BURST_EN Set this bit to enable DMA in links to use burst mode. 12 1 read-write INDSCR_BURST_EN Set this bit to enable DMA out links to use burst mode. 13 1 read-write OUT_DATA_BURST_EN Set this bit to enable DMA burst MODE 14 1 read-write MEM_TRANS_EN 15 1 read-write SEPER_EN Set this bit to use special char to separate the data frame. 16 1 read-write HEAD_EN Set this bit to enable to use head packet before the data frame. 17 1 read-write CRC_REC_EN Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame 18 1 read-write UART_IDLE_EOF_EN Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame. 19 1 read-write LEN_EOF_EN Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame. 20 1 read-write ENCODE_CRC_EN Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1. 21 1 read-write CLK_EN Set this bit to enable clock-gating for read or write registers. 22 1 read-write UART_RX_BRK_EOF_EN Set this bit to enable to use brk char as the end of a data frame. 23 1 read-write INT_RAW 0x4 0x20 RX_START_INT_RAW when a separator char has been send it will produce uhci_rx_start_int interrupt. 0 1 read-only TX_START_INT_RAW when DMA detects a separator char it will produce uhci_tx_start_int interrupt. 1 1 read-only RX_HUNG_INT_RAW when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt. 2 1 read-only TX_HUNG_INT_RAW when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt. 3 1 read-only IN_DONE_INT_RAW when a in link descriptor has been completed it will produce uhci_in_done_int interrupt. 4 1 read-only IN_SUC_EOF_INT_RAW when a data packet has been received it will produce uhci_in_suc_eof_int interrupt. 5 1 read-only IN_ERR_EOF_INT_RAW when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt. 6 1 read-only OUT_DONE_INT_RAW when a out link descriptor is completed it will produce uhci_out_done_int interrupt. 7 1 read-only OUT_EOF_INT_RAW when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt. 8 1 read-only IN_DSCR_ERR_INT_RAW when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt. 9 1 read-only OUT_DSCR_ERR_INT_RAW when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt. 10 1 read-only IN_DSCR_EMPTY_INT_RAW when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt. 11 1 read-only OUTLINK_EOF_ERR_INT_RAW when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt. 12 1 read-only OUT_TOTAL_EOF_INT_RAW When all data have been send it will produce uhci_out_total_eof_int interrupt. 13 1 read-only SEND_S_Q_INT_RAW When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet. 14 1 read-only SEND_A_Q_INT_RAW When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet. 15 1 read-only DMA_INFIFO_FULL_WM_INT_RAW 16 1 read-only INT_ST 0x8 0x20 RX_START_INT_ST 0 1 read-only TX_START_INT_ST 1 1 read-only RX_HUNG_INT_ST 2 1 read-only TX_HUNG_INT_ST 3 1 read-only IN_DONE_INT_ST 4 1 read-only IN_SUC_EOF_INT_ST 5 1 read-only IN_ERR_EOF_INT_ST 6 1 read-only OUT_DONE_INT_ST 7 1 read-only OUT_EOF_INT_ST 8 1 read-only IN_DSCR_ERR_INT_ST 9 1 read-only OUT_DSCR_ERR_INT_ST 10 1 read-only IN_DSCR_EMPTY_INT_ST 11 1 read-only OUTLINK_EOF_ERR_INT_ST 12 1 read-only OUT_TOTAL_EOF_INT_ST 13 1 read-only SEND_S_Q_INT_ST 14 1 read-only SEND_A_Q_INT_ST 15 1 read-only DMA_INFIFO_FULL_WM_INT_ST 16 1 read-only INT_ENA 0xC 0x20 RX_START_INT_ENA 0 1 read-write TX_START_INT_ENA 1 1 read-write RX_HUNG_INT_ENA 2 1 read-write TX_HUNG_INT_ENA 3 1 read-write IN_DONE_INT_ENA 4 1 read-write IN_SUC_EOF_INT_ENA 5 1 read-write IN_ERR_EOF_INT_ENA 6 1 read-write OUT_DONE_INT_ENA 7 1 read-write OUT_EOF_INT_ENA 8 1 read-write IN_DSCR_ERR_INT_ENA 9 1 read-write OUT_DSCR_ERR_INT_ENA 10 1 read-write IN_DSCR_EMPTY_INT_ENA 11 1 read-write OUTLINK_EOF_ERR_INT_ENA 12 1 read-write OUT_TOTAL_EOF_INT_ENA 13 1 read-write SEND_S_Q_INT_ENA 14 1 read-write SEND_A_Q_INT_ENA 15 1 read-write DMA_INFIFO_FULL_WM_INT_ENA 16 1 read-write INT_CLR 0x10 0x20 RX_START_INT_CLR 0 1 write-only TX_START_INT_CLR 1 1 write-only RX_HUNG_INT_CLR 2 1 write-only TX_HUNG_INT_CLR 3 1 write-only IN_DONE_INT_CLR 4 1 write-only IN_SUC_EOF_INT_CLR 5 1 write-only IN_ERR_EOF_INT_CLR 6 1 write-only OUT_DONE_INT_CLR 7 1 write-only OUT_EOF_INT_CLR 8 1 write-only IN_DSCR_ERR_INT_CLR 9 1 write-only OUT_DSCR_ERR_INT_CLR 10 1 write-only IN_DSCR_EMPTY_INT_CLR 11 1 write-only OUTLINK_EOF_ERR_INT_CLR 12 1 write-only OUT_TOTAL_EOF_INT_CLR 13 1 write-only SEND_S_Q_INT_CLR 14 1 write-only SEND_A_Q_INT_CLR 15 1 write-only DMA_INFIFO_FULL_WM_INT_CLR 16 1 write-only DMA_OUT_STATUS 0x14 0x20 0x00000002 OUT_FULL 1:DMA out link descriptor's fifo is full. 0 1 read-only OUT_EMPTY 1:DMA in link descriptor's fifo is empty. 1 1 read-only DMA_OUT_PUSH 0x18 0x20 OUTFIFO_WDATA This is the data need to be pushed into out link descriptor's fifo. 0 9 read-write OUTFIFO_PUSH Set this bit to push data in out link descriptor's fifo. 16 1 read-write DMA_IN_STATUS 0x1C 0x20 0x00000002 IN_FULL 0 1 read-only IN_EMPTY 1 1 read-only RX_ERR_CAUSE This register stores the errors caused in out link descriptor's data packet. 4 3 read-only DMA_IN_POP 0x20 0x20 INFIFO_RDATA This register stores the data pop from in link descriptor's fifo. 0 12 read-only INFIFO_POP Set this bit to pop data in in link descriptor's fifo. 16 1 read-write DMA_OUT_LINK 0x24 0x20 OUTLINK_ADDR This register stores the least 20 bits of the first out link descriptor's address. 0 20 read-write OUTLINK_STOP Set this bit to stop dealing with the out link descriptors. 28 1 read-write OUTLINK_START Set this bit to start dealing with the out link descriptors. 29 1 read-write OUTLINK_RESTART Set this bit to mount on new out link descriptors 30 1 read-write OUTLINK_PARK 1£º the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working. 31 1 read-only DMA_IN_LINK 0x28 0x20 0x00100000 INLINK_ADDR This register stores the least 20 bits of the first in link descriptor's address. 0 20 read-write INLINK_AUTO_RET 1:when a packet is wrong in link descriptor returns to the descriptor which is lately used. 20 1 read-write INLINK_STOP Set this bit to stop dealing with the in link descriptors. 28 1 read-write INLINK_START Set this bit to start dealing with the in link descriptors. 29 1 read-write INLINK_RESTART Set this bit to mount on new in link descriptors 30 1 read-write INLINK_PARK 1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working 31 1 read-only CONF1 0x2C 0x20 0x00000033 CHECK_SUM_EN Set this bit to enable decoder to check check_sum in packet header. 0 1 read-write CHECK_SEQ_EN Set this bit to enable decoder to check seq num in packet header. 1 1 read-write CRC_DISABLE Set this bit to disable crc calculation. 2 1 read-write SAVE_HEAD Set this bit to save packet header . 3 1 read-write TX_CHECK_SUM_RE Set this bit to enable hardware replace check_sum in packet header automatically. 4 1 read-write TX_ACK_NUM_RE Set this bit to enable hardware replace ack num in packet header automatically. 5 1 read-write CHECK_OWNER Set this bit to check the owner bit in link descriptor. 6 1 read-write WAIT_SW_START Set this bit to enable software way to add packet header. 7 1 read-write SW_START Set this bit to start inserting the packet header. 8 1 read-write DMA_INFIFO_FULL_THRS when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt. 9 12 read-write STATE0 0x30 0x20 STATE0 0 32 read-only STATE1 0x34 0x20 STATE1 0 32 read-only DMA_OUT_EOF_DES_ADDR 0x38 0x20 OUT_EOF_DES_ADDR This register stores the address of out link descriptoir when eof bit in this descriptor is 1. 0 32 read-only DMA_IN_SUC_EOF_DES_ADDR 0x3C 0x20 IN_SUC_EOF_DES_ADDR This register stores the address of in link descriptor when eof bit in this descriptor is 1. 0 32 read-only DMA_IN_ERR_EOF_DES_ADDR 0x40 0x20 IN_ERR_EOF_DES_ADDR This register stores the address of in link descriptor when there are some errors in this descriptor. 0 32 read-only DMA_OUT_EOF_BFR_DES_ADDR 0x44 0x20 OUT_EOF_BFR_DES_ADDR This register stores the address of out link descriptor when there are some errors in this descriptor. 0 32 read-only AHB_TEST 0x48 0x20 AHB_TESTMODE bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0) 0 3 read-write AHB_TESTADDR The two bits represent ahb bus address bit[20:19] 4 2 read-write DMA_IN_DSCR 0x4C 0x20 INLINK_DSCR The content of current in link descriptor's third dword 0 32 read-only DMA_IN_DSCR_BF0 0x50 0x20 INLINK_DSCR_BF0 The content of current in link descriptor's first dword 0 32 read-only DMA_IN_DSCR_BF1 0x54 0x20 INLINK_DSCR_BF1 The content of current in link descriptor's second dword 0 32 read-only DMA_OUT_DSCR 0x58 0x20 OUTLINK_DSCR The content of current out link descriptor's third dword 0 32 read-only DMA_OUT_DSCR_BF0 0x5C 0x20 OUTLINK_DSCR_BF0 The content of current out link descriptor's first dword 0 32 read-only DMA_OUT_DSCR_BF1 0x60 0x20 OUTLINK_DSCR_BF1 The content of current out link descriptor's second dword 0 32 read-only ESCAPE_CONF 0x64 0x20 0x00000033 TX_C0_ESC_EN Set this bit to enable 0xc0 char decode when DMA receives data. 0 1 read-write TX_DB_ESC_EN Set this bit to enable 0xdb char decode when DMA receives data. 1 1 read-write TX_11_ESC_EN Set this bit to enable flow control char 0x11 decode when DMA receives data. 2 1 read-write TX_13_ESC_EN Set this bit to enable flow control char 0x13 decode when DMA receives data. 3 1 read-write RX_C0_ESC_EN Set this bit to enable 0xc0 char replace when DMA sends data. 4 1 read-write RX_DB_ESC_EN Set this bit to enable 0xdb char replace when DMA sends data. 5 1 read-write RX_11_ESC_EN Set this bit to enable flow control char 0x11 replace when DMA sends data. 6 1 read-write RX_13_ESC_EN Set this bit to enable flow control char 0x13 replace when DMA sends data. 7 1 read-write HUNG_CONF 0x68 0x20 0x00810810 TXFIFO_TIMEOUT This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt. 0 8 read-write TXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift) 8 3 read-write TXFIFO_TIMEOUT_ENA The enable bit for txfifo receive data timeout 11 1 read-write RXFIFO_TIMEOUT This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt. 12 8 read-write RXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift) 20 3 read-write RXFIFO_TIMEOUT_ENA This is the enable bit for DMA send data timeout 23 1 read-write ACK_NUM 0x6C 0x20 RX_HEAD 0x70 0x20 RX_HEAD This register stores the packet header received by DMA 0 32 read-only QUICK_SENT 0x74 0x20 SINGLE_SEND_NUM The bits are used to choose which short packet 0 3 read-write SINGLE_SEND_EN Set this bit to enable send a short packet 3 1 read-write ALWAYS_SEND_NUM The bits are used to choose which short packet 4 3 read-write ALWAYS_SEND_EN Set this bit to enable continuously send the same short packet 7 1 read-write Q0_WORD0 0x78 0x20 SEND_Q0_WORD0 This register stores the content of short packet's first dword 0 32 read-write Q0_WORD1 0x7C 0x20 SEND_Q0_WORD1 This register stores the content of short packet's second dword 0 32 read-write Q1_WORD0 0x80 0x20 SEND_Q1_WORD0 This register stores the content of short packet's first dword 0 32 read-write Q1_WORD1 0x84 0x20 SEND_Q1_WORD1 This register stores the content of short packet's second dword 0 32 read-write Q2_WORD0 0x88 0x20 SEND_Q2_WORD0 This register stores the content of short packet's first dword 0 32 read-write Q2_WORD1 0x8C 0x20 SEND_Q2_WORD1 This register stores the content of short packet's second dword 0 32 read-write Q3_WORD0 0x90 0x20 SEND_Q3_WORD0 This register stores the content of short packet's first dword 0 32 read-write Q3_WORD1 0x94 0x20 SEND_Q3_WORD1 This register stores the content of short packet's second dword 0 32 read-write Q4_WORD0 0x98 0x20 SEND_Q4_WORD0 This register stores the content of short packet's first dword 0 32 read-write Q4_WORD1 0x9C 0x20 SEND_Q4_WORD1 This register stores the content of short packet's second dword 0 32 read-write Q5_WORD0 0xA0 0x20 SEND_Q5_WORD0 This register stores the content of short packet's first dword 0 32 read-write Q5_WORD1 0xA4 0x20 SEND_Q5_WORD1 This register stores the content of short packet's second dword 0 32 read-write Q6_WORD0 0xA8 0x20 SEND_Q6_WORD0 This register stores the content of short packet's first dword 0 32 read-write Q6_WORD1 0xAC 0x20 SEND_Q6_WORD1 This register stores the content of short packet's second dword 0 32 read-write ESC_CONF0 0xB0 0x20 0x00DCDBC0 SEPER_CHAR This register stores the seperator char seperator char is used to seperate the data frame. 0 8 read-write SEPER_ESC_CHAR0 This register stores thee first char used to replace seperator char in data. 8 8 read-write SEPER_ESC_CHAR1 This register stores the second char used to replace seperator char in data . 0xdc 0xdb replace 0xc0 by default. 16 8 read-write ESC_CONF1 0xB4 0x20 0x00DDDBDB ESC_SEQ0 This register stores the first substitute char used to replace the seperator char. 0 8 read-write ESC_SEQ0_CHAR0 This register stores the first char used to replace reg_esc_seq0 in data. 8 8 read-write ESC_SEQ0_CHAR1 This register stores the second char used to replace the reg_esc_seq0 in data 16 8 read-write ESC_CONF2 0xB8 0x20 0x00DEDB11 ESC_SEQ1 This register stores the flow control char to turn on the flow_control 0 8 read-write ESC_SEQ1_CHAR0 This register stores the first char used to replace the reg_esc_seq1 in data. 8 8 read-write ESC_SEQ1_CHAR1 This register stores the second char used to replace the reg_esc_seq1 in data. 16 8 read-write ESC_CONF3 0xBC 0x20 0x00DFDB13 ESC_SEQ2 This register stores the flow_control char to turn off the flow_control 0 8 read-write ESC_SEQ2_CHAR0 This register stores the first char used to replace the reg_esc_seq2 in data. 8 8 read-write ESC_SEQ2_CHAR1 This register stores the second char used to replace the reg_esc_seq2 in data. 16 8 read-write PKT_THRES 0xC0 0x20 0x00000080 PKT_THRS when the amount of packet payload is greater than this value the process of receiving data is done. 0 13 read-write DATE 0xFC 0x20 0x16041001 DATE version information 0 32 read-write UHCI1 Universal Host Controller Interface 0x3FF4C000 UHCI1 13